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[Axi] interpretation of Axi protocol atomic access

2022-06-25 23:29:00 【myhhhhhhhh】

Reading AXI Protocol atomic access

One 、 Write it at the front

AXI agreement Compare with UART,SPI,I2C Come on , Whether it's Both the content and the difficulty have reached a higher level , It is quite necessary to interpret it in an article Length is too long , therefore , of AXI Something in common 、 General questions , The author alone prefixes 【AXI】 The title of the is concatenated in a small range , Finally, it's summed up as To interpret in a simple way AXI agreement , And From scratch Verilog AXI Protocol design , This is the order in which the author thinks and tests , Just look 【AXI】 Every article of , Many readers may feel some doubt about seeing the leopard from the inside , But if you wait until the author finishes this column , Read from beginning to end , There should be a quick harvest and understanding .

Two 、 Reading AXI Atomic access to protocols

The content of this discussion , Atomic access , It's actually a number IC In chip design Combination of software and hardware A good example of , If the reader is Software background , Then the concept must be familiar , Whether it's NV Of CUDA still Intel Of CPU, Include Various high-level programming languages , Such as C# and JAVA This concept appears in many . The most important part of understanding atomic access is for AXI Agreement AxLOCK The understanding of this set of signals , Of course , Atomic access to this part AXI3.0 and AXI4.0 There's also a big difference in , What will be discussed later is more about from AXI4.0 From the angle of Of .

The name of the atomized access , In fact, it vividly describes its meaning , Atoms are usually indivisible , Reflected in atomic access , It's also Reflect its indivisible characteristics , For what is indivisible ？

We will have a paragraph 32bit The address of , As an atom , That doesn't mean that during this part of the time when the atomized access is performed , The data corresponding to this part of the address cannot be changed （ Like follow burst The operator wants to change its height alone 16 position , Or individually change its low 16 position , Isn't that equivalent to taking the atoms apart ）, It must be seen as a whole .

2.1 AXI The size of the atom in the protocol

What a big address , Can be in AXI As in the agreement The smallest atomic unit Well ？ Used in the agreement “single copy atomicity size” To express the concept , The complexity of peripherals is different , So for different peripherals “single copy atomicity size” It is also obvious that , For more complex equipment , Usually used “single copy atomicity size” by 64 bits, And for simpler devices , The use of “single copy atomicity size” by 32 bits that will do . The following pictures can well illustrate 64bits And 32bits The division principle of .

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2.2 Signal list

2.2.1 AXI3.0 edition AxLOCK Signal list

AxLOCK[1:0]	Access Type
0b00	Normal access
0b01	Exclusive access
0b10	Locked access
0b11	Reserved

2.2.2 AXI4.0 edition AxLOCK Signal list

AxLOCK	Access Type
0b0	Normal access
0b1	Exclusive access

stay AXI4.0 in ,ARM Cancelled. Yes Locked access Support for , Keep only Normal access and exclusive access Two forms of access . Therefore, we will discuss more about Normal access and Exclusive access These two ways

2.2.3 Feedback signal xRESP

Here comes xRESP, In fact, it means RRESP and BRESP These two signals ,RRESP[1:0] Is for AXI agreement Feedback signal of read operation （ Read data path ）,BRESP[1:0] Is for AXI agreement Feedback signal of write operation （ Write reply path ）. The four states are shown in the table below , But in the course of discussing atomization , In fact, we only need to understand OKAY and EXOKAY These two states are sufficient .

xRESP[1:0]	Response	Description
0b00	OKAY	Normal visit (Normal access) success
0b01	EXOKAY	Exclusive access (Exclusive access okay) success
0b10	SLVERR	Slave device error
0b11	DECERR	Decoder error

2.2.3.1 Reading OKAY The signal

OKAY The signal is for most transaction Feedback signal of operation , Return to OKAY There may be the following situations

normal access success
exclusive access Failure
For the main equipment to Slave devices that do not support exclusive operations send out exclusive access Access to the feedback

2.2.3.2 Reading EXOKAY The signal

if xRESP feedback EXOKAY This signal , There is only one possibility , Namely Exclusive access (Exclusive access) success .

2.3 Exclusive access （Exclusive accesses）

2.3.1 Exclusive access process

The master device is for an address , perform Read operation , among AxLOCK Set to Exclusive access , The slave device starts to monitor the address signal after step 1 .
A span after , The master device is for the same address , Conduct “ Write operations ”, among AxLOCK Also set to Exclusive access , Step 2 AWID Need and step one ARID Match .
Feedback signal ：
success (EXOKAY)！ It means during this period of time , No, The other master device attempts to change the address locked in the read operation in step 1 , Then the exclusive write operation in step 2 can be updated memory
Failure (OKAY)! It means during this period of time , There are other main devices Changed the address locked in the first read operation of step , that memory Can't update

2.3.2 Exclusive access requirements

Exclusive accesses New requirements are put forward for the hardware of the slave device , Generally, it is new Added one monitor To monitor From the master device transaction Transmission signal , If other master devices do not operate on the address during this period , All's well that ends well , Update the data corresponding to the address , But if Exclusive access failed ,monitor Will go to Block the master device from writing this address , And return the feedback to the main equipment ( such as CPU), such ,CPU Reassign the address according to your own requirements or try again after a period of time , In this way , We guarantee the whole process of reading and writing , Software knows “ Is there only one thread （Master） Writing this address （ Other threads can read in this process ）”, Avoid conflicts between threads .
Of course, there are the following requirements for exclusive access

1 ARID And AWID It needs to be the same
2 Read and write addresses ,burst size、burst length、 Other control signals need to remain the same
3 Exclusive access burst lentgh transfer No more than 16
4 The address of exclusive transmission needs to be aligned transaction The total number of bytes
5 AxCACHE The signal needs to ensure that the slave device in monitoring status can receive transaction（ In other words AxCACHE It can't be Cacheable Of ）

2.3 Normal visit (Normal accesses)

In the state of normal access , No, monitor, No monitoring , according to burst Mechanism of burst transmission , That is to say, in the simplest case , Reading and writing memory Data is enough .

2.4 From what AXI3 To AXI4 To cancel the Locked Type？

The reason why we are talking about atomization , In fact, it is to avoid multi-threaded conflicts , So in a simpler way , Lock this address directly , Only one fixed master is allowed to operate it , Access to any other device is denied , At the hardware level, thread interlocking is implemented in a more simple and crude way , Is it feasible ？
It must be possible , This is the same. AXI3 in Locked Type The functions you want to achieve , Only when Unlock signal When we arrive , Other devices can access this address , But this way Great impact on Performance （ Long time occupation of special address , Unlock only after complete , Only when the comparison is written, judge whether the update is feasible, and then give feedback to the main equipment ）, therefore To cancel the Locked Type.