FPGA - 7 Series FPGA selectio -01- introduction and DCI technology introduction

SelectIO brief introduction

FPGA Of SelectIO Namely I/O Interface and I/O General term of logic .Xilinx SelectIO Support multiple level standards , except MIPI C-PHY level （ Three level standard ） Outside ,IO Can be directly connected 3.3V as well as 3.3V The following basic all level standards , Preliminary statistical support 72 Different level standards . At the same time, it is often necessary to configure the level standard and... According to the specific application design IO To configure , Excerpts of this article are translated from UG471 Chapter one of , Yes 7 Series of FPGA Of SelectIO Brief introduction to resources and numerical control impedance (DCI) Introduction to technology .

7 series FPGA I/O Bank Supported features

all 7 series FPGA There are configurable SelectIO Driver and receiver , Support multiple standard interfaces . The powerful function set includes programmable control of output strength and swing rate , Using digital control impedance (DCI) On chip terminal for , And internally generated reference voltage (INTERNAL_VREF) The ability of .

HR Bank No, DCI.DCI It doesn't apply to HR Bank. With some exceptions , Every I/O Library contains 50 individual SelectIO Pin . The two pins at the end of each library can only be used for single ended I/O standard . The rest 48 Pins of can use single ended or differential standards , Use two SelectIO The pins consist of positive / negative （P/N） Yes , Available for single ended or differential standards . Every SelectIO Resources all contain inputs 、 Output and tristate drivers .

7 series FPGA Of HR and HP I/O Bank The functions supported are as follows ：

Feature	HP I/O Banks	HR I/O Banks
3.3V I/O standard	N/A	Supported
2.5V I/O standards	N/A	Supported
1.8V I/O standards	Supported	Supported
1.5V I/O standards	Supported	Supported
1.35V I/O standards	Supported	Supported
1.2V I/O standards	Supported	Supported
LVDS signaling	Supported	Supported
24 mA drive option for LVCMOS18 and LVTTL outputs	N/A	Supported
V CCAUX_IO supply rail	Supported	N/A
Digitally-controlled impedance (DCI) and DCI cascading	Supported	N/A
Internal VREF	Supported	Supported
Internal differential termination (DIFF_TERM)	Supported	Supported
IDELAY	Supported	Supported
ODELAY	Supported	N/A
IDELAYCTRL	Supported	Supported
ISERDES	Supported	Supported
OSERDES	Supported	Supported
ZHOLD_DELAY	N/A	Supported

Single ended and differential logic architecture

SelectIO The pins can be configured in various ways I/O standard , Including single ended and differential .

• Single ended I/O standard （ Such as LVCMOS、LVTTL、HSTL、PCI and SSTL）.
• Difference I/O standard （ for example ,LVDS、Mini_LVDS、RSDS、PPDS、BLVDS Sum and difference HSTL and SSTL).

Configured to be different I/O Standard pins , The input and output of the port are also connected in different ways .

The following figure shows a single ended （ only ）HP I/O Bank（IOB) And its connection to internal logic and device pads .

The following figure shows the general HP IO Bank And its connection to internal logic and device pads .

The following figure shows a single ended （ only ) Of HR IO Bank And its connection to internal logic and device pads .

The following figure shows the general HR IO Bank And its connection to internal logic and device pads .

Through comparative analysis, it is known that , stay HP and HR I/O Bank in , Single ended and conventional IO Bank Basically the same , Except single ended IOB A signal that is not connected to produce a differential output .HR and HP comparison , Except for the lack of DCI On chip terminal enable control , Other structures are basically similar .

In most devices , Single ended IOB Is located in each I/O Two pins at both ends of the group . Form a group of others 48 General of pins IOB Single ended and differential I/O standard . Every IOB There is a direct connection to ILOGIC/OLOGIC Yes , Contains input and output logic resources for data and tristate . Every IOB There is one with ILOGIC/OLOGIC Direct connection to , Contains IOB Data and input and output logic resources of tristate control , For data and IOB Three state control of .ILOGIC and OLOGIC Can be configured to ISERDES and OSERDES.

General design criteria

This section summarizes the use of 7 series FPGA Of SelectIO General guidelines to consider when designing resources . stay 7 In a series of devices , One I/O Library from 50 individual IOB form .Bank The number of depends on the device size and package pins . stay 7 series FPGA In summary , Usable I/O The total number of libraries is listed by device type . Usable I/O The total number of libraries is listed by device type . for example ,XC7K325T Yes 10 A usable I/O library .

choice IO Supply voltage of the pin

VCCO

VCCO The power supply is 7 series I/O The main power supply of the circuit . A given I/O All of the groups VCCO The pins must be connected to the same external power supply on the circuit board , therefore , A given I/O All in the group I/O Must share the same VCCO level .VCCO The voltage must correspond to the voltage assigned to I/O Of the group I/O Standard requirements . incorrect VCCO Voltage may cause loss of function or equipment damage . stay HP I/O Bank in , If I/O Standard voltage requirements <1.8V, But the application VCCO>2.5V, The device will automatically enter the overvoltage protection mode . Use the right VCCO Level reconfiguration device , You can get back to work .

VREF

Single ended with differential input buffer I/O The standard requires an input reference voltage （VREF）. When one I/O Within the group VREF when , The group's two multifunction VREF Pins must be used as VREF Power input .7 series FPGA You can do this by enabling INTERNAL_VREF Constraints to choose to use internally generated reference voltages .

VCCAUX

Global assistance (VCCAUX) The power supply is mainly used for 7 series FPGA The interconnection logic of various internal block features provides power . stay I/O In the library ,VCCAUX Also used for some I/O The standard input buffer circuit supplies power . These include all 1.8V Or less I/O standard , As well as some 2.5V standard （ only HR I/O Bank）. Besides ,VCCAUX Is used for difference and VREF I/O The standard group differential input buffer circuit provides power .

VCCAUX_IO

auxiliary I/O（VCCAUX_IO） The power supply only exists in HP I/O In the library , by I/O The circuit supplies power .Kintex-7 and Virtex-7 FPGAs The data table contains a " Maximum physical interface of the memory interface （PHY） rate " Table for , It says VCCAUX_IO. The table indicates VCCAUX_IO How the pins are in 1.8V（ Default ） Or optional 2.0V Lower power supply , To achieve higher frequency performance for certain types of memory interfaces . Although this table is designed for memory interface , But it can also be used for other high-speed single ended interfaces according to the target bit rate VCCAUX_IO Power supply provides guidance .

** This table does not apply to LVDS, because LVDS The drive circuit used is different from the single ended drive , suffer VCCAUX_IO The level has a great influence .** therefore , about LVDS Interface ,VCCAUX_IO It doesn't matter at which voltage level the rail is powered .1.8V The default value of provides low power consumption , And in I/O Provides very close to the same performance . When the fastest bit rate supported by a single ended drive requires a slight increase in performance , You can choose 2.0V.I/O The network and primitives have a called VCCAUX_IO Design constraints , If any bank Of VCCAUX_IO The pin is set to 2.0V, The constraint should be specified in the design .

During and after configuration I/O state

7 series FPGA Have a special purpose for I/O bank 0 The pins of the configuration function contained in .Bank 14 and 15 It also contains pins called multi-function or multi-purpose pins I/O Pin , It can also be used to configure , But it is converted to normal after configuration I/O Pin . Besides , stay SSI In the device ,bank 11、12、17、18、20 and 21 Pins in have limitations during configuration similar to multi-function pins . However , On these pins bank There is no configuration function .

stay bank 14 and / or bank 15 yes HR bank And configured as VCCO requirement < 1.8V In our devices , If the input is connected to 0 Or suspended and configured with voltage > 2.5V, During configuration, the input may be from 0-1-0 Switch to interconnect logic .

only HP bank Available in DCI

Numerical control impedance (DCI) Technology is introduced

With FPGA Getting bigger and bigger , The system clock speed is getting faster and faster ,PCB The design and manufacture of plates become more difficult . As the edge rate gets faster , Maintaining signal integrity becomes a key issue . PCB Board wiring must be properly terminated to avoid reflection or ringing . To terminate the trace , Traditionally, resistors are added to make the output and / Or the input impedance matches the impedance of the receiver or driver to the impedance of the trace . However , Due to the device I/O An increase in , Adding resistors near the device pins will increase the board area and the number of components , And in some cases it may be physically impossible . In order to solve these problems and achieve better signal integrity ,Xilinx The numerical control impedance (DCI) technology .

according to I/O standard ,DCI The output impedance of the driver can be controlled , It can also be in the drive and / Or add a parallel terminal to the receiver , To precisely match the characteristic impedance of the transmission line . DCI Take the initiative to adjust I/O These internal impedances , Place in... With calibration VRN and VRP External precision reference resistor on the pin . This can compensate for the I/O Impedance change . It also continuously adjusts the impedance to compensate for changes in temperature and supply voltage fluctuations .

For drives with controlled impedance I/O standard ,DCI Control the driver impedance to match the two reference resistors , Or for some standards , Match half of these reference resistor values .
For... With controlled parallel terminals I/O standard ,DCI Provide parallel terminals for transmitter and receiver . This eliminates the need for termination resistors on the board , The circuit board wiring difficulty and the number of components are reduced , The signal integrity is improved by eliminating the stub reflection . When the terminal resistance is too far away from the end of the transmission line , A stub reflection will occur . Use DCI, The terminating resistor shall be as close to the output driver or input buffer as possible , So as to eliminate the stub reflection . DCI Only in 7 series FPGA HP I/O bank Available in the , stay HR I/O bank Unavailable in .

Xilinx DCI

DCI At every I/O bank Two multi-purpose reference pins are used to control the impedance of the driver or the bank All in I/O Parallel terminal value of . N Reference pin (VRN) It must be pulled up to... Through the reference resistor VCCO, and P Reference pin (VRP) It must be pulled down to ground through another reference resistor . The value of each reference resistance shall be equal to PCB The characteristic impedance of the board wiring or twice this value .

To be used in the design DCI：

1. stay HP I/O bank The distribution of DCI I/O One of the standards .
2. take VRN The multifunction pin is connected to a precision resistor , The resistor is connected to the same group of VCCO .
3. take VRP The multi-function pin is connected to a precision resistor grounded .

The following sections discuss how to determine the differences I/O The standard VRN and VRP Precision resistance value of . Every bank Use only one set VRN and VRP resistance , So every bank In all of the DCI The standard must be able to share the same external resistance value . If the same I/O bank Multiple in the column I/O bank Use DCI, And all of this I/O bank Use the same VRN/VRP Resistance value , Inside VRN and VRP Nodes can be cascaded , There is only one pair Whole I/O All in column I/O bank All pins need to be connected to precision resistors . This option is called DCI cascade . If... Is not used in the group DCI I/O standard , Then these pins can be used as regular I/O Pin .

DCI By selectively opening or closing I/O To adjust I/O The impedance of . Adjust the impedance to match the external reference resistance . The adjustment starts during the equipment startup sequence . By default , Before the first part of the impedance adjustment process is completed ,DONE The pin does not go high .

DCI Calibration can be done by example DCIRESET Primitive to reset . When the equipment is running RST Enter to switch to DCIRESET The original language , Reset DCI State machine and restart the calibration process . stay DCIRESET Modular LOCKED Before the output is asserted , All use DCI Of I/O Will not be available . This function operates at temperature and / Or the supply voltage is very useful in applications where the device is powered on to a significant change in nominal operating conditions .

For controlled impedance output drivers , The impedance can be adjusted to match the reference resistor or half the resistance of the reference resistor . For on-chip termination , The termination is always adjusted to match the reference resistance .
For support DCI Control of the impedance driver I/O standard ,DCI You can configure the output driver to the following types ：

• Controlled impedance driver （ The source terminal is connected ）, Controlled Impedance Driver (Source Termination)
• With half impedance （ The source terminal is connected ） Controlled impedance driver ,Controlled Impedance Driver with Half Impedance (Source Termination)

For those that support parallel termination I/O standard ,DCI Create a and VCCO/2 Thevenin resistance equivalent to voltage level or separate termination resistance . I/O The standard naming convention adds ：

• If I/O There is always a separation terminal resistance in the , It's in I/O Add... To the standard name DCI, Whether the standard is used for input 、 Output or bidirectional port .
• I/O In the standard name T_DCI, If the separation terminal resistance exists only when the output buffer is in three states .

Match_cycle configuration option

Match_cycle Is a configuration option , Can be found in FPGA Optionally pause the start sequence at the end of the configuration sequence , until DCI The logic performs the first match to the external reference resistor （ calibration ）. This option is sometimes referred to as DCI matching .

DCIUpdateMode configuration option

DCIUpdateMode Is a configuration option , Can be overwritten on DCI Circuit update and VRN and VRP Frequency control of impedance matched by reference resistance . This option defaults to AsRequired, But in Xilinx There is also an optional value in the implementation software Quiet.** It is strongly recommended that DCIUpdateMode The options remain the default AsRequired, In order to allow DCI The circuit operates normally .**DCIUpdateMode The configuration options are set as follows ：

• AsRequired： Perform initial impedance calibration during device initialization , Dynamic impedance adjustment shall be carried out as required during the whole equipment operation （ Default ）.
• Continuous： about 7 series FPGA, This value is not valid （ The default is AsRequired）.
• Quiet： Impedance calibration is performed only once during device initialization , Or for a design that contains the primitive , Each time the DCIRESET The primitive asserts RST One time for pin .

DCIRESET The original language

DCIRESET yes Xilinx Design primitives , It provides the ability to execute during normal operation of the design DCI The ability to reset the controller state machine . Unless DCIUpdateMode Set to Quiet Or for the and use settings outlined below, use DCI The multi-function pins of , in the majority of cases , This primitive is not required in the design .

some Bank Special DCI requirement

If I/O bank 14 or 15（ Any device ） or bank 11、12、17、18、20 and 21（ Limited to SSI equipment ） Any multi-function pin in is assigned DCI I /O Standards in user design ,DCIRESET Primitives should also be included in the design and used . under these circumstances , The design should be pulsed DCIRESET Of RST Input , And then wait LOCKED The signal is asserted , Then use the DCI Standard for any user input or output on these pins . This is necessary , Because of these I/O The pin ignores the initialization that occurs during normal device initialization DCI calibration .

therefore , If not used DCIRESET Primitive and DCIUpdateMode Set to AsRequired, These pins become normal I/O After the pin , At the end of configuration and DCI The calibration algorithm updates these pins DCI There is an indefinite delay between settings . If not used DCIRESET also DCIUpdateMode Set to Quiet, Then these pins will never be set DCI value . under these circumstances , Controlled impedance DCI I/O standard （ for example LVDCI_18） It will always act as if it is in a high resistance state , And split the terminal DCI I/O standard （ for example SSTL15_DCI） It will behave as if there is no internal termination resistance . Include and use in the design DCIRESET Primitive allows these pins to have DCI I/O Standards and can be implemented without problems .

DCI cascade

Use DCI I/O The standard 7 series FPGA HP I/O bank You can choose from another HP I/O bank export DCI Impedance value . As shown in the figure below , The digital control bus is internally distributed throughout bank in , To control each I/O The impedance of .

about DCI cascade , One I/O bank（ Lord bank） It must be VRN/VRP The pin is connected to an external reference resistor . same HP I/O bank Column （ Slave Library ） In the other I/O bank You can use... With the same impedance as the main library DCI standard , There is no need to remove these from the library VRN/VRP The pin is connected to an external resistor . In a cascade group DCI Impedance control from I/O The primary group receives .

The following figure shows a comparison of multiple I/O bank Of DCI Cascading support . Bank B It is the Lord. I/O bank, and Bank A and C It is thought to be from I/O bank.

Use DCI The guidelines for cascading are as follows ：

• DCI Cascading can only be done through HP I/O bank Column usage .
• Master and slave SelectIO bank Must all reside on the same device HP I/O On the column , And can span the entire column , Unless there is an inserter boundary .
• DCI Cascades cannot be interconnected by using stacked silicon (SSI) The larger the technology Virtex-7 Intermediate layer boundary of device . This includes XC7V2000T and XC7VX1140T device .
• Master and slave I/O bank Must have the same VCCO and VREF（ If applicable ） voltage .
• same HP I/O Columns are not used DCI（ Straight through bank） Of I/O bank You don't have to obey VCCO and VREF Voltage rules DCI Set up .
• All masters bank And from the bank Must satisfy DCI I/O bank compatibility rules （ for example , All master and slave libraries are allowed to use only one single terminal type DCI I/O standard ）.
• To locate in the same I/O In column I/O bank, Refer to the UG475.
• Specific information about implementing DC cascading in the design , Refer to the UG471 Of 46 page DCI_CASCADE constraint .
• Xilinx It is recommended that the unused bank Also power on , Because the unused I/O bank Of VCCO Pin suspension will lower these pins and bank Medium I/O Pin of ESD Protection level . If bank Not powered on ,DCI It can still pass through the non powered bank cascade .

Controlled impedance driver （ Source termination ）

To optimize signal integrity for high-speed or high-performance applications , Additional measures are required to match the output impedance of the driver with the impedance of the transmission line and the receiver . Ideally , The output impedance of the driver must match the characteristic impedance of the drive line , Otherwise, reflection will occur due to discontinuity . To solve this problem , Designers sometimes use close to high strength 、 External source series termination resistance of low impedance driver pin . Select resistance value , Make the sum of the output impedance of the driver and the resistance of the source series terminal approximately equal to the impedance of the transmission line .

DCI A controlled impedance output driver can be provided to eliminate reflections , Without the use of external source termination resistors . The impedance is set by an external reference resistor , Its resistance is equal to the line impedance .

Support controlled impedance driver DCI I/O Standard has ：LVDCI_15、LVDCI_18、HSLVDCI_15、HSLVDCI_18、HSUL_12_DCI and DIFF_HSUL_12_DCI.
The following figure illustrates 7 Controlled impedance driver in series devices .

With half impedance （ The source terminal is connected ） Controllable impedance driver

DCI It also provides half the reference resistor impedance for the driver . Doubling the reference resistance value can reduce the static power consumption of these resistors by half . Support for controlled impedance drivers with half impedance DCI I/O The standard is LVDCI_DV2_15 and LVDCI_DV2_18.

The figure below illustrates a 7 Series devices have a controlled driver with half impedance inside . Reference resistance R It has to be for 2 × Z0 To match Z0 The impedance of .

Split-Termination DCI（ Thevenin equivalent terminal to VCCO/2）

some I/O standard （ for example HSTL and SSTL） The input terminal resistance is required Connect to VCCO/2 Of VTT voltage , See the picture below .

Split terminal DCI Use two resistance values (2R) Double the resistor to create a Thevenin equivalent circuit . A connection to VCCO, The other is connected to the ground . Using this method , Separate the termination DCI Provide with VCCO/2 Equivalent termination .2R The termination resistance is set by an external reference resistor . for example , To achieve 50Ω to VCCO/2 Thevenin equivalent parallel termination circuit , Need to be in VRN and VRP Use... On pins 100Ω External precision resistor . Supports separate termination DCI The input criteria are shown in the following table .

HSTL_I_DCI	DIFF_HSTL_I_DCI	SSTL18_I_DCI	DIFF_SSTL18_I_DCI
HSTL_I_DCI_18	DIFF_HSTL_I_DCI_18	SSTL18_II_DCI	DIFF_SSTL18_II_DCI
HSTL_II_DCI	DIFF_HSTL_II_DCI	SSTL18_II_T_DCI	DIFF_SSTL18_II_T_DCI
HSTL_II_DCI_18	DIFF_HSTL_II_DCI_18	SSTL15_DCI	DIFF_SSTL15_DCI
HSTL_II_T_DCI	DIFF_HSTL_II_T_DCI	SSTL15_T_DCI	DIFF_SSTL15_T_DCI
HSTL_II_T_DCI_18	DIFF_HSTL_II_T_DCI_18	SSTL135_DCI	DIFF_SSTL135_DCI
		SSTL135_T_DCI	DIFF_SSTL135_T_DCI
		SSTL12_DCI	DIFF_SSTL12_DCI
		SSTL12_T_DCI	DIFF_SSTL12_T_DCI

The following figure illustrates 7 Separate terminal in series equipment DCI.

VRN/VRP External resistance design migration guide

Previously had DCI Of Xilinx FPGA The series uses slightly different circuits to calibrate from those placed in VRN and VRP Separate terminal impedance of the external reference resistor on the pin . Virtex-6 FPGA DCI Calibrate each branch of the separate termination circuit to twice the external resistance value . for example , In possession of 50Ω To VCCO/2 Of the target parallel terminal Virtex-6 In the device ,VRN and VRP The pin requires 50Ω External resistor .

7 series FPGA DCI Calibrate each branch of the separate termination circuit , Make it directly equal to the external resistance value . for example , In possession of 50Ω To VCCO/2 Of the target parallel terminal 7 In a series of devices ,VRN and VRP The pin requires 100Ω External resistor .

Under controlled impedance DCI And separate termination DCI The standard selection should be in the same I/O Group （ Or multiple cascades DCI Group ） Used in VRN and VRP When the value of , It is particularly important to consider this .
In have for LVDCI_18 Output 50Ω Target controlled impedance driver and for HSTL_I_DCI_18 Input 50Ω Target separation terminal receiver Virtex-6 FPGA In design , have access to VRN and VRP On the pin 50Ω External resistors to achieve . Migrate the same design to 7 series FPGA Will not change HSTL_I_DCI_18 I/O standard ; however , The external resistor must be changed to 100Ω, And the controlled impedance driver is changed to LVDCI_DIV2_18 Output . The result of this example is equivalent ; however , Resistance value and I/O Standards need to be changed . VRN and VRP External resistors can be used safely 0.05W Or higher rated power .

DCI and 3-state DCI (T_DCI)

SSTL and HSTL I/O The standard I Class driver version only supports one-way signaling ; They can only be assigned to input only or output only pins in the design , Not bi-directional pins . I class SSTL and HSTL I/O The standard DCI Version is only entered in （ Not output ） There is an internal separation terminal resistor on the . Support two-way and one-way signaling SSTL and HSTL I/O The standard II Class driver version ; They can be assigned to inputs in the design 、 Output or bidirectional pin . II class SSTL and HSTL I/O The standard DCI Version is always entered 、 There is an internal separation terminal resistance on the output or bidirectional pin . The following figure illustrates 7 Series devices have separate terminal drivers inside .

When there is a separation terminal when driving ,DCI Only control the impedance of the terminal , Without controlling the drive . However , Many applications can benefit from turning off separate terminating resistors while pin driving . Tristate DCI (T_DCI) The standard is intended to meet this requirement by turning off the separate termination resistor when the output buffer is driven , And turn on the separation terminal resistor when the output is in three states （ For example, when Receive or be idle ）. T_DCI The standard can only be assigned to bidirectional pins . For unidirectional input pins , Standard... Can be assigned DCI edition . For unidirectional output pins , Can assign non DCI or DCI edition .

With always present breakaway terminations DCI Of a resistor I/O The standard is shown in the following table .

HSTL_I_DCI	DIFF_HSTL_I_DCI	SSTL18_I_DCI	DIFF_SSTL18_I_DCI
HSTL_I_DCI_18	DIFF_HSTL_I_DCI_18	SSTL18_II_DCI	DIFF_SSTL18_II_DCI
HSTL_II_DCI	DIFF_HSTL_II_DCI	SSTL15_DCI	DIFF_SSTL15_DCI
HSTL_II_DCI_18	DIFF_HSTL_II_DCI_18	SSTL135_DCI	DIFF_SSTL135_DCI
		SSTL12_DCI	DIFF_SSTL12_DCI

It has separate termination only in three states DCI Of I/O standard ：

HSTL_II_T_DCI	SSTL18_II_T_DCI	DIFF_SSTL18_II_T_DCI
HSTL_II_T_DCI_18	SSTL15_T_DCI	DIFF_SSTL15_T_DCI
DIFF_HSTL_II__T_DCI	SSTL135_T_DCI	DIFF_SSTL135_T_DCI
DIFF_HSTL_II_T_DCI_18	SSTL12_T_DCI	DIFF_SSTL12_T_DCI

all 7 Series equipment DCI I/O standard ：

LVDCI_18	HSTL_I_DCI	DIFF_HSTL_I_DCI	SSTL18_I_DCI	DIFF_SSTL18_I_DCI
LVDCI_15	HSTL_I_DCI_18	DIFF_HSTL_I_DCI_18	SSTL18_II_DCI	DIFF_SSTL18_II_DCI
LVDCI_DV2_18	HSTL_II_DCI	DIFF_HSTL_II_DCI	SSTL18_II_T_DCI	DIFF_SSTL18_II_T_DCI
LVDCI_DV2_15	HSTL_II_DCI_18	DIFF_HSTL_II_DCI_18	SSTL15_DCI	DIFF_SSTL15_DCI
HSLVDCI_18	HSTL_II_T_DCI	DIFF_HSTL_II_T_DCI	SSTL15_T_DCI	DIFF_SSTL15_T_DCI
HSLVDCI_15	HSTL_II_T_DCI_18	DIFF_HSTL_II_T_DCI_18	SSTL135_DCI	DIFF_SSTL135_DCI
			SSTL135_T_DCI	DIFF_SSTL135_T_DCI
			SSTL12_DCI	DIFF_SSTL12_DCI
			SSTL12_T_DCI	DIFF_SSTL12_T_DCI
			HSUL_12_DCI	DIFF_HSUL_12_DCI

To be in 7 Correct use in series devices DCI：

1. VCCO The pins must be in accordance with this I/O bank Medium IOSTANDARD Connect to the appropriate VCCO voltage .

2. The correct... Must be used in the software DCI I/O Buffer , The method is to use IOSTANDARD Attribute or HDL Instantiation in code .

3. DCI The standard requires that an external reference resistor be connected to a multipurpose pin （VRN and VRP）. When needed , These two multi-purpose pins cannot be used DCI Of I/O bank In general I/O, Or cascade DCI Time master I/O bank In general I/O. Pin VRN It must be pulled up to... Through its reference resistance VCCO. Pin VRP It must be pulled down to ground through its reference resistance . In from I/O bank Intermediate League DCI when , There is one exception to this requirement , because VRN and VRP Pins can be used for general purpose I/O.

With controlled impedance driver DCI The standard can be used for input signals only . In this case , If these pins are given I/O bank The only use in DCI Standard pins , Then bank It is not necessary to connect the external reference resistor to VRP/VRN Pin . When these are based on DCI Of I/O The standard is bank The only criterion in , The bank Medium VRP and VRN Pins can be used for general purpose I/O.

• VRP/VRN There is no need for a reference resistor DCI Enter as shown in the following table .

LVDCI_18	LVDCI_DV2_18	HSLVDCI_18	HSUL_12_DCI
LVDCI_15	LVDCI_DV2_15	HSLVDCI_15	DIFF_HSUL_12_DCI

4. The value of the external reference resistor should be selected , To provide the required output driver impedance or shunt terminal impedance . for example , When using LVDCI_15 when , To achieve 50Ω Output driver impedance ,VRN and VRP The external reference resistors used on the pins should each be 50Ω. Use SSTL15_T_DCI when , To achieve 50Ω Thevenin Equivalent termination To VCCO/2, The external reference resistance shall be 100Ω, namely (2R). Xilinx Ask for in VRP and VRN Use exactly the same resistance value on the pins , To achieve the desired DCI Behavior .
5. follow DCI I/O Bank The rules ：

• Use DCI When cascading ,VREF Must be the same as I/O bank Or a group I/O bank All inputs in are compatible .
• VCCO Must be the same as I/O bank All inputs and outputs in are compatible .
• Separate the termination 、 The controlled impedance driver and the controlled impedance driver with half impedance can coexist in the same group .

DCI Usage Examples

The following figure provides instructions for using HSTL_I_DCI and HSTL_II_DCI I/O Examples of standards .

The following figure provides instructions for using SSTL18_I_DCI and SSTL18_II_DCI I/O Examples of standards .

HR I/O Bank Uncalibrated split terminals in (IN_TERM)

HR I/O bank There is an optional on-chip separation terminal feature , And HP I/O bank Three state separation terminal in DCI The characteristics are very similar . And HP Three state separation termination in the group DCI similar ,HR The options in the group create a Thevenin equivalent circuit using two internal resistors with twice the target resistance value . A resistor is terminated to VCCO, The other end is connected to ground , Is the midpoint VCCO/2 Provide Thevenin equivalent termination circuit . When the output buffer is in three states , There are always terminations on the input and bi-directional pins . However , This uncalibrated split terminal option and three state split terminal DCI An important difference between them is , In the use of DCI when , This function is not calibrated to VRN and VRP External reference resistor on the pin , Instead, an internal resistance without a calibration routine is called to calibrate the compensation temperature 、 Process or voltage changes . The target Thevenin equivalent resistance value for this option is 40Ω、50Ω and 60Ω.

And DCI Another difference between terminals is how to call this uncalibrated terminal in the design . Although through will T_DCI I/O Criteria assigned to HP I/O bank Medium I/O Pin to call the three state separation terminal DCI Options , But by putting IN_TERM Constraints are assigned to I/O Pin to call the uncalibrated separation terminal option HR I/O bank The Internet in . This can be done in many ways , Included in the source HDL In design 、 stay UCF、NCF or XCF In file , Or in the PlanAhead In software .

reference

1. UG471