How high does UART baud rate require for clock accuracy?

A serial port communication （UART） It is an asynchronous communication , Both the sender and the receiver need to communicate according to the agreed baud rate . When baud rate error occurs , It will cause communication error . What are the factors that cause baud rate error , Today, let's analyze .

1. Frequency division error

First , The baud rate is generated according to the frequency division of the system clock , The relationship between the system clock and baud rate may not be an integer multiple , Therefore, there will be errors in frequency division . But now most of them MCU The system clock of is relatively high , Usually in the tens of MHz, Far greater than the baud rate of serial communication , So the effect of this error is very small . hypothesis MCU The clock is 48MHz, The baud rate is 115200,48MHz/115200=416.67, according to 417 frequency division , The actual baud rate is 48M/417=115108, Error is （115200-115108）/115200, about 0.08%, This error is very small , No effect on serial communication .

however , When the system clock is low , Or when the baud rate is high , That is, the difference ratio between the two is small , This error cannot be ignored .

For some earlier 51 Kernel MCU, Due to low operating frequency , Non integer crystal oscillator （ such as 11.0592M etc. ） To use the common baud rate （ such as 9600、115200）, The error of frequency division shall be as small as possible .

2. Clock error

secondly , The main error of baud rate depends on the error of system clock . How high is the requirement for clock error in serial communication ？

First look at the serial port communication sequence diagram ：

The serial port communication consists of the starting bit 、 Data bits 、 Check bit 、 Stop bit composition . With the common 8N1 For example , namely 1 Bit start bit ,8 Digit bit , No verification ,1 Bit stop bit . That is to say, transferring a byte requires 10bits. Each byte has a start bit for synchronization , So the error will only accumulate in one byte .

It's not hard to see. , At the last bit sampling , Maximum error , The allowable limit error is 0.5 position . Per byte 10 Bit calculation , The maximum allowable error is ±0.5/10=±0.05, namely ±5%. Considering that the serial communication involves both ends of the transceiver , There may be errors at both ends , therefore , The error at each end should be controlled within ±2.5% within .

When data bit 、 When there are many parity bits, etc , The required clock error is higher . Considering the above-mentioned frequency division error , Generally speaking , The clock error is less than ±2% when , Serial communication is reliable .

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