Learning methods of zynq

ZYNQ As the current hot SOC Class processor , It is being used by more and more companies . Study ZYNQ My friends are more and more many , Beginners may think ZYNQ It's hard to learn , I only learned 51, Or even even even 51 Never learned , At the sight of ZYNQ I was confused . Actually , Everything is difficult at the beginning , As long as you know how , Learn from good examples ZYNQ, It's very simple , Here we summarize our study ZYNQ Some of them should spot ：

1. A practical development board .

This is the basis of the experiment , Sometimes the software simulation passes , It's not always possible to run on the board , And there's a development board in hand , What East Xidu can be seen intuitively , The effect is not comparable by simulation . But the development board should not be more , If you have more, you don't even know which to learn , sleep This is ok , That's good, too , Then learn this for half a day , That study for a long time , The result is to learn something different . It's better to end , By the end One learns another .

2. Mastery method , Study hard and think carefully .

ZYNQ Not monsters , Don't be afraid of difficulties ,ZYNQ Learning is the same as ordinary single chip computers , The basic method is ：

3. understand ZYNQ Basic structure .

Study ZYNQ You need to be right before ZYNQ Have a general understanding of its basic structure and functions , Such as PS、AXI Bus 、 PLL PLL、 FIFO etc. . Need to know PLL It is used to generate clocks of different frequencies , If you use WM8960（ Audio codec chip ） You need to generate 12MHz The clock of ;FIFO It is used for data caching and asynchronous clock domain data transmission .

4. understand Verilog HDL Basic grammar

Hardware without software is like walking dead . Software is the soul of hardware , Hardware is the stage of software . Only good software design can make The performance of hardware , And the essence of software is code . Study FPGA In the same way ,Verilog HDL As a hardware description language , It's right A description of a digital circuit , Digital circuits work in parallel , So I'm writing Verilog HDL We should have the idea of parallelism , Different from software Design language , Software design language is composed of CPU Unified treatment , Serial operation of one instruction , So software design language is the base The design idea of serial , So I'm writing Verilog HDL Pay attention to this difference when coding . In addition to Verilog HDL Basic syntax It must be mastered , As commonly used module/endmodule、input/output/inout、wire/reg、begin/end、posedge/negedge、 always/assign、if/else、case/default/endcase/parameter/localparam And other keywords should be clear about their functions and differences . Mastered Verilog HDL The basic grammar and Verilog HDL After the idea of concurrent design , Will feel Verilog HDL and C Language is as simple .

5. ZYNQ PS Learning from

Study ZYNQ PS First of all, understand C The basic grammar of language . Then understand PS End basic system framework and peripherals , for example PS End frame structure 、 On chip interconnection 、AXI Bus 、DDR Controller and so on . The key is PS Terminal C Program . Software systems can be considered to be built on A stack on a hardware based system , Or a series of layers , From the bottom to the top is the basic hardware system （ come from Vivado Custom hard Pieces of ）、 Board level support package 、Operating System、 Software applications . Beginners can see more official documents and materials , about PS End of the software ,xilinx Provides a wealth of library functions , A lot of the time users Just call it directly , Readers should learn to use these library functions . When there is a problem , Readers can use xilinx Of SDK Various in the development environment Debug functions to locate errors , To help solve the problem .

6. Think more , Do more .

Practice makes perfect , Cooked first , Caiqiao . How to get familiar with ？ It's up to everyone to do it by themselves , Practice more , Just look or say nothing It's too much to use . Only in use ZYNQ In the process of , Will be a little familiar , Only hands-on practice , To be able to FPGA There are practical feel .

After getting familiar with it , We should think further , That is the so-called coincidence . We provide dozens of routines , For everyone to learn , Follow the routine , nothing Non is familiarity ZYNQ The process of , Only further thinking , In order to better grasp ZYNQ, That is to say, draw inferences from one instance . Routine is dead , Man is alive. , therefore , It can be based on routines , Free play , Realize more other functions , And summarize the rules , For future study and Lay a solid foundation for use , such , Before you can get it at your fingertips .

therefore , You must learn by yourself , Just watch the video , Just look at the documents , You can't . A simple example , You watch the video , Teach you how to cook , It's estimated that you'll learn in a few minutes . In fact, you can test it yourself , Whether it can be cooked well ？ Opportunities are always reserved for those who are prepared , Only Usually make more preparations , To seize the opportunity .