Digital IC code -- traffic lights

subject

describe
A traffic light is required , It has three small red, yellow and green indicators and a pedestrian button , Under normal circumstances , The motorway indicator light shall be in accordance with 60 Clock cycle green ,5 A clock cycle yellow light ,10 A clock cycle, a red light cycle . When the pedestrian button is pressed , If the remaining green time is greater than 10 A clock , Is shortened to 10 A clock , Less than 10 The two clocks remain the same .
The signal interface diagram of the module is as follows ：

Please use VerilogHDL Language implementation , And write testbench Verification function .

Code

Design

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, // Ectopic reset signal , Low level active 
        input clk, // Clock signal 
        input pass_request,
		output reg [7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
    parameter RED=0;
    parameter GREEN=1;
    parameter YELLOW=2;
    reg [1:0] state,next_state;
	//60 clk green
	//5 clk yellow
	//10 clk red
    [email protected](posedge clk,negedge rst_n)
        if(~rst_n)
            state<=RED;
        else
            state<=next_state;
    [email protected](*)
    begin
        case(state)
            RED:if(clock==1)
                    next_state=GREEN;
                else
                    next_state=RED;
            YELLOW:if(clock==1)
                      next_state=RED;
                   else
                       next_state=YELLOW;
            GREEN:if(clock==1)
                     next_state=YELLOW;
                  else
                      next_state=GREEN;
            default:next_state=RED;
        endcase
    end
    //led
    [email protected](*)
        case(state)
            RED:{
    red,yellow,green}=3'b100;
            YELLOW:{
    red,yellow,green}=3'b010;
            GREEN:{
    red,yellow,green}=3'b001;
            default:{
    red,yellow,green}=3'b000;
        endcase
    //clock
    [email protected](posedge clk,negedge rst_n)
        if(~rst_n)
            clock<=10;                       //red
        else
            case(state)
                RED:if(clock==1)
                         clock<=60;
                    else
                         clock<=clock-1;
                YELLOW:if(clock==1)
                            clock<=10;
                       else
                            clock<=clock-1;
                GREEN:
                      if(pass_request)
                          if(clock>10)
                              clock<=10;
                          else
                              clock<=clock-1;
                      else if(clock==1)
                          clock<=5;
                      else
                          clock<=clock-1;
                default:clock<=10;
            endcase
endmodule

Test platform

module test;
reg clk;
reg rst_n;
reg pass_request;
wire [7:0] clock;
wire red;
wire yellow;
wire green;
//clk
initial
begin
   clk=0;
   forever
      #5 clk=~clk;
end
//rst_n
initial
begin
    rst_n=0;
	#100
	rst_n=1;
end
//
initial
begin
   pass_request=0;
   //
   repeat(20)
      @(posedge clk);
   wait(green&&clock==18);
   pass_request<=1;
   @(posedge clk);
   pass_request<=0;
   //
   repeat(40)
      @(posedge clk);
   wait(green&&clock==9);
   pass_request<=1;
   @(posedge clk)
   pass_request<=0;
end

//inst
triffic_light U
    (.*
	/* input rst_n, // Ectopic reset signal , Low level active  input clk, // Clock signal  input pass_request, output reg [7:0]clock, output reg red, output reg yellow, output reg green */
    );
endmodule

result

Under normal circumstances , A green light 60 A cycle , Yellow light 5 A cycle , A red light 10 A cycle

Green and greater than 10 A cycle , Pedestrian press

Green light and less than or equal to 10 A cycle , Pedestrian press