Door level modeling - learning notes

The type of door

• Logic circuits can be designed using logic gates .Verilog The language predefines some logic gates , To support users to use .
• Basic logic gates fall into two categories ：
  • And / Or category （and/or）
  • Buffer / Non category （buf/not）

And gate and or gate

• And gate 、 Or gates have one scalar output and multiple scalar inputs .

• Congeneric and / Or the terms of a category ：

  • and And gate
  • or Or gate
  • xor Exclusive OR gate
  • nand NAND gate
  • nor Or not
  • xnor xnor

• The logical symbols are as follows
  

• Its truth table
  

• Verilog Instance reference

  //  Define port 
  wire OUT,IN1,IN2;
  //  Instance reference of basic door 
  and	a1(OUT,IN1,IN2);
  nand na1(OUT,IN1,IN2);
  or or1(OUT,IN1,IN2);
  nor	nor1(OUT,IN1,IN2);
  xor x1(OUT,IN1,IN2);
  xnor nx1(OUT,IN1,IN2);
  
  //  More than two , Three input NAND gate 
  nand nal_3inp(OUT,IN1,IN2,IN3);
  
  // Instance reference door , Do not name the instance , It's also legal 
  and (OUT,IN1,IN2);
  
  

Buffer / Not gate

• buf/not A gate has one scalar input and multiple scalar outputs （ And and/or Opposite door ）. We only discuss one input and one output buf/not door , For... With multiple outputs , The values at all outputs are the same .

• The terms of two basic gates

  • buf
  • not

• Logical symbols
  

• Truth table
  

• Be careful ：buf and not Can have multiple output ports , But there can only be one input port , The input port must be the last in the port list .

• Instance reference

  buf b1(OUT1,IN);
  not n1(OUT1,IN);
  
  //  Two output ports 
  buf b1_2out(OUT1,OUT2,IN);
  
  //  Instance unnamed reference , legal 
  not (OUT1,IN);
  

• Buffer and not gate with control end (bufif/notif)

  • 4 One with control signal port buf/not door

    • bufif1
    • bufif0
    • notif1
    • notif0

  • Data can only be transmitted if the control signal is valid , If the control end is invalid , The output is high impedance z.

  • Logical symbols
    

  • Truth table

  • Instance reference

    bufif1 b1(out, in ,ctrl);	
    bufif0 b0(out, in ,ctrl);		
    
    notif1 n1(out, in ,ctrl);
    notif0 n0(out, in ,ctrl);
    

• In some cases , For example, when a signal is driven by multiple drivers , When we design the driver , Stagger the effective time of control signals , Avoid one signal line being driven by two sources at the same time . At this time, a buffer with a control end is required / It is not the door that makes the circuit .

Design examples

• Gate multiplexer

  • Design a 4-out-of-1 multi-channel selector with two bit selection signal , Suppose the strobe signal s1 and s0 Not for x or z value , The structure diagram and truth table are as follows
    
  • Several basic types of logic gates can be used to implement multiplexers
    
  • Verilog Realization
    
  • RTL View
    
  • Write simulation excitation module
    
  • Simulation results
    

• Four bit pulse carry full adder

  • Implement a pulse carry adder , Its basic component is a full adder , The mathematical expression of the full adder is as follows ： $$sum=(a\otimes b\otimes cin)$$$$cout=(a\cdot b)+cin\cdot (a\otimes b)$$

  • Logic diagram of one bit full adder
    

  • One full adder Verilog describe
    

  • The four bit pulse carry full adder can be composed of four one bit full adders , Here's the picture
    

  • Verilog Realization
    

  • Simulation stimulation

    `timescale 1ns/1ps
    
    module fulladd4_tb();
    
    reg	[3:0]	A,B;
    reg 			C_IN;
    wire	[3:0]	SUM;
    wire			C_OUT;
    
    fulladd4 FAL_4(SUM, C_OUT, A, B, C_IN);
    
    //  Set signal monitoring 
    initial
    begin
    	$monitor($time,"A=%b,B=%b,C_IN=%b, --- C_OUT=%b,SUM=%b\n", A,B,C_IN,C_OUT,SUM);
    end
    
    //  Input excitation signal 
    initial
    begin
    	A=4'd0;
    	B=4'd0;
    	C_IN=1'b0;
    	
    	#5 A=4'd3;
    		B=4'd4;
    	
    	#5 A=4'd2;
    	   B=4'd5;
    	
    	#5 A=4'd9;
    		B=4'd9;
    	
    	#5 A=4'd10;
    		B=4'd15;
    		
    	#5 A=4'd10;
    		B=4'd5;
    		C_IN=1'b1;
    end
    endmodule
    

  • Simulation results
    

Gate delay

• The circuits described above are all delay free （ Zero Delay ）. however , In the actual circuit , Any logic gate has a delay .Verilog The gate delay can be used to describe the delay in the logic circuit .

Three delays

• Rise delay ： When the input of the door changes , The output of the door is from 0,x,z Change to 1 Time required .
  
• Descent delay ： The output of the door is from 1,x,z Change to 0 Time required .
  
• Shutdown delay ： Refers to the output of the door from 0,1,x Change to high impedance z Time required .
• Be careful ：
  • If the value changes to an uncertain value x, Then the learned time can be regarded as the one with the smallest of the above three delay values .
• There are three different ways to explain the delay of the gate
  • Specify only one , This value is used for all types of delay ;
  • Specify two （ Rise and fall ）, Then the turn-off delay is the smallest of the two ;
  • Designate three , That is, each delay indicates .
    

Minimum / A typical / Maximum delay

• In addition to specifying the three types of delays described above , The minimum delay can also be specified for each type of delay 、 Maximum and typical values . The user can decide which delay to use at the beginning of the simulation .
• Illustrate with examples
  

Design examples