[tinyriscv verilator] branch transplanted to Da Vinci development board of punctual atom

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Preface
In order to complete their own design , Have to use OpenOCD As host computer , Under test RISC-V Single step debugging and GDB Debugging and other operations , Then I took a look tinyriscv-verilator Our debugging module supports these operations , So let's transplant this version tinyriscv, Record on a blog .

Some basic operations will not be repeated here , No, readers can go to my other blog ： Teach you how to transplant tinyriscv To FPGA On https://blog.csdn.net/qq_44447544/article/details/123251073

One 、 Download the source code

Code cloud link ：https://gitee.com/liangkangnan/tinyriscv/tree/verilator/
Package and download , After decompressing , take RTL Add to the new project source code . When I'm done , As shown in the figure below ：

You can see jtag Debug module updated , take tap、dtm、dmi as well as dm Modules are implemented independently .

Two 、 Migration to Aritx-7

Development board ; Punctual atom Da Vinci FPGA Development board （v1）, The chip model is xc7a35tfgg484-1
The debugger ：FT4232H

2.1 add to mmcm IP
stay tinyriscv_soc_top.sv Instantiated in the top-level module mmcm IP, So add , Click on the IP Catalog, Search for Clocking, Select the one shown in the figure below IP：

The configuration is shown in the figure below ;

And then click ok, Pop up window to select Generate.

You can see this IP It's no longer missing .

2.2 Pin restraint

First, let's take a look at this version of tinyriscv Top level interface for ：

You can see the sum master The version is almost the same , Removed the separate UART Pins, take UART The function is placed in GPIO In the reuse function . If the pin is constrained , The clock is bound to the clock pin of the board , The reset button is constrained to the button ,halted_ind_pin Signals and dump_wave_en_o The signals are constrained to LED On ,jtag、gpio and flash spi Are constrained to idle IO You can go up. .

Constraint file ：

#  Clock constraint 50MHz, Duty cycle 50%
create_clock -period 20.000 -name sys_clk_pin -waveform {0.000 10.000} -add [get_ports clk_50m_i]

#  Clock pin 
set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports clk_50m_i]

#  Reset pin 
set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports rst_ext_ni]

# CPU Stop the indicating pin ,halted_ind_pin  by 1 Effective when , Lighten up led2
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports halted_ind_pin]

# io_pins Pin 
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {io_pins[0]}]
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {io_pins[1]}]
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {io_pins[2]}]
set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33} [get_ports {io_pins[3]}]
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports {io_pins[4]}]
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {io_pins[5]}]
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {io_pins[6]}]
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {io_pins[7]}]
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports {io_pins[8]}]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {io_pins[9]}]
set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {io_pins[10]}]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {io_pins[11]}]
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {io_pins[12]}]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports {io_pins[13]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {io_pins[14]}]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {io_pins[15]}]

# JTAG TCK Pin   PortA 0
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports jtag_TCK_pin]
create_clock -period 300.000 -name jtag_clk_pin [get_ports jtag_TCK_pin]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_pin]

# JTAG TMS Pin  PortA 3
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports jtag_TMS_pin]

# JTAG TDI Pin  PortA 1
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports jtag_TDI_pin]

# JTAG TDO Pin  PortA 2
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports jtag_TDO_pin]

# SPI dq Pin 
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {flash_spi_dq_pin[0]}]
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {flash_spi_dq_pin[1]}]
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {flash_spi_dq_pin[2]}]
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {flash_spi_dq_pin[3]}]

# SPI SS Pin 
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports flash_spi_ss_pin]

# SPI CLK Pin 
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports flash_spi_clk_pin]

#SPI  Related settings 
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

2.3 Comprehensive realization

After the pin is restrained , Carry out comprehensive implementation , The layout is as follows ：

Resource utilization ;

3、 ... and 、 A simple test

The generated bitstream is downloaded to the development board , And then through OpenOCD Connect .

You can see that you have successfully connected to . Then log in to the terminal to try single step debugging and breakpoint ：

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