(5) SPI application design and simulation verification 3 - verification code implementation

（ 3、 ... and ） Verification code
         Design finished Master End sum Slave End code , We need to validate the function block , Check if it works properly .Testbanch The design of is mainly divided into several main parts ：
        ①  Declare the port type （ Input and output variables of the module ）;
        ②  Generate clock , According to what you set , Here we use 200Mhz Of clk, So a cycle is 5ns, Then every time 2.5ns A numerical inversion is required ;
        ③  Generate driver （ Give the data ）, First reset The initial value and then the value , Here we need to define some task, To generate values in the desired format ;
        ④  Definition task, This is in uart There are also ;
        ⑤  Define the detection module , Judge what you read read_data Whether it is consistent with the entered value , To judge SPI Whether the overall design OK;
        ⑥  Instantiation master and slave

1） Code implementation

module test;
    reg        clk_200mhz;
    reg        rstn;
    reg[11:0]  cmd_in;
    reg        cmd_valid;
    wire       cmd_ready;
    wire       sclk,csn,mosi,miso;
    wire       read_data;

//(1)reset clk&rstn 
initial begin
    clk_200mhz    = 0;
    rstn          = 0;
    #10;
    rstn          = 1;
end

//(2)generate clk
always    #2.5 clk