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How to import matlab data into modelsim simulation
2022-07-30 07:35:00 【FPGA - Signal Processing】
目的
This method is mainly applicable to matlab和modelsimUseful for co-simulation,比如matlab生成的adc数据作为modelsim during simulationadcIncentive data,或者modelsim生成的ramData can also be loaded during simulationmodelsim进行仿真,下面我们将以matlab生成adc原始数据导入modelsim来演示.
matlab代码
生成adc数据的代码:
clc;
clear all;
close all;
fs = 250e6; % adc采样率
fout = 10e6; % Generate signal frequency
len = 8192; % Generate signal length
t = 0:1/fs:(len-1)/fs; % The time slice of the sampling point
amp = 25000; % adc信号幅度
adc_dat = cos(2*pi*fout*t); % adc数据
adc_dat = awgn(adc_dat, 40);% Add noise to the resulting signal
adc_dat = round(adc_dat*amp);% 量化adc数据
% Plot the time and frequency domains of the signal
subplot(211);
plot(adc_dat);
subplot(212);
fft_data = abs(fft(adc_dat, len));
fft_data = 20*log10(fft_data);
fft_data = fft_data - max(fft_data);
plot(fft_data);
% 存储ADC数据
u_adc_dat = sign2com(adc_dat, 16);
fp = fopen('adc_dat.bin', 'w');
fprintf(fp, '%04x\n',u_adc_dat);
fclose all;
adcFrequency and time domain plots of the data
- verilog代码
`timescale 1ns/1ps
module testbench();
localparam LEN = 8192 ;
reg [15:0] adc_dat[8191:0] ;
reg clk ;
reg rst ;
reg [12:0] cnt ;
reg [15:0] sim_dat ;
initial begin
$readmemh("./adc_dat.bin", adc_dat, 0, LEN-1);
end
initial begin
clk = 0;
rst = 1;
cnt = 0;
sim_dat = 0;
#1000;
rst = 0;
end
always #2.00 clk = ~clk ;
[email protected](posedge clk)
begin
if(rst) begin
cnt <= 0;
end
else begin
cnt <= cnt + 1;
sim_dat <= adc_dat[cnt];
end
end
endmodule
- 仿真效果
- 总结
This method works very wellmatlabThe generated data serves as a stimulus source.Replace the module that needs to generate the data source inside the module.
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