Connection design and test platform -- Summary of SystemVerilog interface knowledge points

1、 Why do I need an interface ？

stay SystemVerilog in , In order to simplify the connection between modules 、 With the complexity of the design of a large number of ports 、 Repeated declaration and connection of signals at different design levels , utilize The interface acts as a communication module between blocks To achieve this goal .

advantage ： Concise and not easy to make mistakes , When adding a new signal, you only need to change the module of the interface .

2、 What is an interface ？

It is a structure that represents a bundle of wires , Code with intelligent synchronization and connection function .（ According to my own understanding , It is equivalent to putting the ports between the two modules in the same structure , Avoid repeated statements ）

for example ： If interface is not used , Both the arbiter and the test platform need to declare for the same signal . as follows

// Arbiter model using ports 
module arb_port(input logic[1:0] grant,output logic[1:0] request...);

// In the test platform using ports , You also need to define ports for the same signal 
module test(input logic[1:0] grant,output logic[1:0] request...)

3、 Specifically, how to use interfaces to replace ？--interface

// for example , Simple interface of arbiter 
interface arb_if(input bit clk);
    logic [1:0] grant,request;
    logic rst;
endinterface

// Arbiter with simple interface 
module arb(arb_if arbif);
...
    always @(posedge arbif.clk or posedge arbif.rst) // Can be called directly 
    begin 
...
endmodule

Obvious , After defining the interface, there is no need to set the interface in the arbiter module The statement is made. , The call of signal can be directly used . Add the port name .( for example ：.clk)（ I think it's like adjusting an attribute value ）

  notes ： The clock can be part of the interface or an independent port , And the shorter the instance name of the interface, the better , Easy to quote . It is worth noting that , Interface signals must be driven using non blocking assignment .

4、 Use modport Group the signals in the interface and specify the direction

for example ：

interface arb_if(input bit clk);
    logic [1:0] grant,request;
    logic rst;
    modport TEST(output request,rst,input grant,clk);
    // This declares the direction of the signal 
    ...

endinterface

// Corresponding , In the use of the test platform , It needs to be indicated at the head of the module , There is no need to specify 
module test (arb_if.TEST arbif);