Verilog daily question (vl24 multi bit MUX synchronizer cross time domain output)

Title Description

         stay data_en For the high period ,data_in Will remain unchanged ,data_en Keep at least 3 individual B Clock cycle . indicate , When data_en For the high time , Data can be synchronized .

         In this question data_in The frequency of data change at the end is very low , The change between two adjacent data , At least at intervals 10 individual B Clock cycle .

The interface of the circuit is shown in the figure below . The port description is shown in the table below .

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Problem solving ：

         The general idea of this question is to A Clock domain input signal , Synchronize to B Time domain , With B The rising edge of the clock comes and outputs . The idea here is to A The clock sets a valid signal data_en, When data_en When it is valid for three cycles ,data_out Read data_in Value , Realize an output across the clock domain .

Rounding out the following ：

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg   [3:0] 	dataout
);
    integer i; // Define a parameter to shoot 
    always @(posedge clk_b or negedge brstn) begin
        if(!arstn)  dataout <= 0; 
        else if(i>=4)   dataout <= data_in;
        else dataout <= dataout; // When data_en Low power level ,dataout remain unchanged , Instead of zeroing （ I made a mistake at first ）
    end
                              
    always @(posedge clk_a or negedge arstn)begin
        if(!brstn)  i<=0;
        else if(data_en)  i <= i+1; // Three a After the cycle ,i=4, Need full 3 A cycle ;
        else i <= 0; // Low level  i Zeroing , Wait for re counting 
    end  
                              
                              
endmodule

The idea here is to declare a parameter i Come and shoot , Looking at others' answers , It's interesting to see a method, which is worth learning ：

...
else if(data_en) 
data_a <= {data_a[11:0],data_in}; // Shooting , Using shift register 
...
dataout <= data_a[15:12]; 
// Highest output 4 position , That is, it can be output only after three beats , And when en Low power level , No displacement 
// To enter a new value, you need to shift it three times , It meets the requirements of the topic very well 
...

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The end!