Verilog daily question (vl26 simple stopwatch)

Title Description

Please write a module , Realize the function of simple stopwatch ： With two outputs , When the output port second from 1-60 Cycle count , whenever second Count to 60, Output port minute Add one , Until minute=60, Pause counting .

The interface signal diagram of the module is as follows ：

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Problem solving ：

The idea of this question is relatively simple ,second Count from 1 To 60 loop , full 60minute Into the 1, When minute Carry to 60 when , Another rising edge ,second Zeroing ,minute Do not change until the zero signal arrives .

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin  // Set low level to zero 
            second = 0;
            minute = 0;
        end
        else if(minute == 6'd60) begin // Judgment is minute No when full 60, full 60 be minute unchanged ,second Zeroing 
            second = 0; minute = 60;
        end
        else if(second == 6'd60) begin //second full 60 To the next counting cycle ,minute+1
            second = 1;
            minute = minute+1;
        end
        else second = second + 1;         
        
    end
    
	
	
endmodule

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