Hongke shares | how to test and verify complex FPGA designs (1) -- entity or block oriented simulation

stay IP In the process of nuclear development , Faced with many key technologies , such as IP Nuclear specifications 、 Interface based design 、IP Nuclear test access structure standard 、IP Nuclear verification and packaging . about IP Nuclear verification , It is mainly to establish reference models and test platforms , Then carry out regression test and formal verification . The model referenced here is mainly used to verify the system function and RTL Comparison and verification of the model , This model mainly uses Verilog HDL Wait for language to construct . The establishment of the test platform is in parallel with the design of sub modules , Build verification environment and develop test cases , And aim at IP The behavior level model of the core debugs the test environment and test cases , So that the synchronization is ready for simulation test RTL level IP Nuclear verification environment and test cases .

Simulation and verification are the basis for developing any high-quality FPGA Of RTL The basis of the coding process . In this series of articles , We will share the key steps in our design process ：

• Entity oriented / Simulation of blocks ： By generating excitation on each input signal and verifying RTL Does the code behave as expected , For each IP Different modules of the core carry entities / Simulation of blocks .
• Global oriented simulation ： Once different modules are individually verified , It means that the next step will be the whole IP The simulation is a single UUT（ Tested unit ）.
• (On) Hardware testing ： Although the extended simulation plan provides good credibility , But there are still many corner Cannot be verified in a virtual environment . For these cases , Need a hardware based test plan , This is also the last step to achieve high-quality results .

In this article , We will describe the first step ：IP How the entity or block level of simulation is completed .

“ Entity or block oriented simulation ” This step means that the validation is in IP Correct operation of specific entities or modules with specific operations in the core . Every IP Nuclei are made up of many entities or blocks , To test them , Each entity will have different test platforms , Execute the design by observing the output of the design when the input is stimulated . This will help check the expected behavior .

Take an example to understand everything well . under these circumstances , We will explain our Ethernet switch IP Core filter database .

Filter database storage MAC Address and related information to make frame forwarding decisions . It is a hash based memory , Each address entry has some storage for filtering data bin. The hash algorithm also generates an index that filters the database memory .

There are three main processes for filtering database execution ： Study 、 Search and aging .
• The learning process is responsible for saving frames when different conditions are met .
• The search process is to search in the filter database and obtain the forwarding port mask of the frame .
• The aging process deletes the old according to the given time period MAC entry .

In this simulation MAC In the specific case of table , Always try to test all the mechanisms that make up the filtering database function . In this sense , It's like learning different MAC, Different queries 、 Aging is done in parallel , Finally, it needs to be cleared MAC Table and verify that all entries have been deleted . Besides , Study and always be able to test possible corner Cases are also very important .

Testing and verification are complex FPGA The second key step of the design will be introduced in the following updated articles . Once formed IP All entities of the nuclear work as expected , Global simulation will work .