[SystemVerilog interface] ~ interface

1. Interface interface

1.1 What is an interface ？

1.2 Why use interfaces （ advantage ）？

answer ： Interface It can bring a lot of convenience , It's like Java The same as objects in , It only needs to be defined once , It can be used as an example when necessary . No interface , But if our needs change , There are too many things we need to change , Not conducive to maintenance .

1.3 Illustrate with examples

For example, we need to test Arbiter This module .

Implement with interface ：

1.4 The definition and use of interface

1.4.1 practice

1. Which statements can be in interface As defined in ？
   answer ： Parameters 、 I / O port 、 Functions and tasks 、 Procedure statement block .

2. module in 90% Above in interface All of them apply to , So what's the difference ？
   answer ：module We can exemplify module and interface, however interface Can only be instantiated interface, Cannot instantiate module.

I hope I can hold on , Keep on learning ！ If it works , Would like to pay attention to likes and comments , Neverlost ！！！

Statement ： For reference only , Invasion and deletion ！！！

reference

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