Network equipment hard core technology insider router Chapter 18 dpdk and its prequel (III)

We found that , In these issues , We mentioned repeatedly cache.

Cache refer to CPU Internal cache . This concept is a combination of DRAM At the same time .

Let's review 《 Fundamentals of digital electronic technology 》 in , About RAM Chapter of ——

SRAM Of S, Is static (static) It means , It's also synchronous (Sync) It means . Synchronization refers to ,CPU adopt WR or RD Line direction RAM Send a read-write signal ,RAM Immediately according to Address The address of the line , and Data Line data , Write content to the inside , Or change the internal content from data Line feedback to CPU.SRAM Inside each bit from 6 Transistor composition , As shown in the figure below ：

Another kind RAM be called DRAM,D by Dymanic Abbreviation .DRAM Each bit It only needs 1 A transistor , As shown in the figure below ：

obviously ,DRAM Than SRAM The cost is low , Low power consumption , High integration .

Mr. Lu Xun pointed out ： There are no two sweet sugarcane in the world .DRAM The cost of saving costs and power consumption is ,CPU visit DRAM Time for , About to visit SRAM The time of the 10-100 times .

To make up for it CPU and DRAM Performance loss caused by working speed difference , Engineers are again CPU and DRAM A layer is designed between SRAM, It's called cache (cache).SRAM Its working principle is to use temporal locality and spatial locality .

What is temporal locality ？ In short , After a piece of memory is accessed , In the near future , It has a high probability of being visited again , The probability of being visited decreases with time .

such as ,XX Students let A After the technician pinches his feet , Next time, come to the pedicure shop , Still looking A Technicians have a high probability of pinching their feet ……

such as , My little sister let Tony After the teacher does the hairstyle , Next time, come to the barber shop , Still looking Tony The probability of teachers is relatively high ……

What is spatial locality ？ In short , After a piece of memory is accessed , Its adjacent memory area also has a relatively high probability of being accessed again , The probability of being visited decreases as the offset increases .

such as ,XX After my classmates went to the foot shop , The probability of going to the health care products store next door is relatively high ……

such as , Little sister has been to Tony After the teacher's barber shop , The probability of going to the milk tea shop next door is relatively high ……

Get down to business . Time locality determines Cache The effectiveness of the mechanism ： If the low-speed memory , Just visited the content , Temporarily stored in high-speed memory , that , Because the system has a high probability of accessing these contents next time , This can greatly improve the performance of the system .

And spatial locality determines cache Organization style ： If the contents in the low-speed memory , In blocks of a certain size , Stored in high-speed memory , And the storage order is the same , that , Because the system has a high probability of accessing adjacent content , This can also greatly improve the performance of the system .

In red “ In blocks of a certain size ”, It refers to the cache organization we have repeatedly mentioned ——Cacheline.

Cacheline And primary storage through fully associative mapping 、 Direct mapping or group associative mapping .

Fully associative mapping refers to , Any main memory block can be mapped to any cacheline, However, due to the need to introduce CAM The mechanism of , The cost rises sharply .

Direct mapping refers to , Any main memory block , Can only be mapped to one cacheline, If two main memory blocks are mapped to the same cache line, And frequently used , It's going to happen cache ping-pong The phenomenon of .

Group associative mapping is a balanced design mechanism , A main memory block can be stored in a unique Cache Any line in the group . In practice , This method is more common .

Let's get back to the point , stay DPDK in , in the light of Cache Optimization of is the highlight . Starting tomorrow , We are right. DPDK Make a comprehensive introduction .