Network equipment hard core technology insider router Chapter 17 dpdk and its prequel (II)

yesterday , We see , The emergence of multi-core processors has greatly improved the throughput of soft forwarding , But the optimization of cache has become the bottleneck of multi-core . In addition to the MBUF In addition to being optimized , There's another important thing —— Optimization of counters .

Whether it's a switch , Or routers , An important function is the interface counter .

You can see that in the picture , Each interface on the router has a count of the number of packets sent and received , And byte count . Because the data packets of each interface may be processed by any processor core , We need to think about ： If each processor core operates on the counter ,CPU What happens inside ？

If the processor core A from RAM Read this counter , And add a number , meanwhile , Processor core B It is also necessary to accumulate this counter . therefore , The two processors collide . To solve this problem ,CPU Provides a locking mechanism , But in this way ……

All processor cores have to queue up when processing counters , Processing efficiency is conceivable .

therefore , Engineers assigned a set of counters to each core , Each core processes a packet , Are accumulated on their own counters , Accumulate when the check counter instruction is executed . such , It perfectly solves the problems mentioned above .

Of course , Because the network processor based on multi-core has some special acceleration coprocessors for network processing , Such as Parser( Message parser ), It can read the front of the packet 64 byte , And read the second layer address according to the preset register value 、 Third floor address 、TCP/UDP Port number and other information , hold CPU The core time is liberated from the repetitive parsing of packets , It also greatly accelerates the processing of data packets . Under the blessing of these factors ,8 nucleus 32 Threads do 10M The above pps It is not difficult to .

The words are divided into two parts , Each table a .

Intel To give up IXP NP After the product line , Witness MIPS/ARM stay 10Gbps To 100Gbps The network equipment market of , You can imagine the bitterness in your heart . however , Due to Intel led x86 The system has natural limitations ……

Let us Pull the timeline back to the little dark room of the Stanford professors and their wives .

be based on X86 The initial implementation of the router of the processor is shown in the figure above . as time goes on , Shared PCI The bus evolved into point-to-point PCI-E Bus .

actually , Because the network card has long supported DMA, All packets received by the network card can be written directly RAM in , The problem lies in the later process .

We know , stay DMA After completion , The network card will send CPU The core initiates the interrupt .CPU One of the core processing interrupts , Interrupt the original process , Go into kernel state , Access the packets received by the network card , And copy it to the user status , Back to the operating system . There are three questions ：

1. Interrupting the original process will cause instruction cache cacheline miss.
2. Copying packets to user mode will waste a lot of time .
3. Returning to the original operating system will cause instruction cache cacheline miss.

DPDK By solving these problems , Greatly improved Intel The processor is in Linux Packet processing performance under .

We mentioned repeatedly cache, So far , It is necessary to insert a special issue , Have a good chat about this thing , because , This concept will also be mentioned many times in the following hard core technology insider of computing and storage devices ……