Makefile notes (Yiwen Institute makefile)

There are countless source files in a project , By type 、 function 、 Modules are placed in several directories ,Makefile Defines a set of rules for which files to compile first , Which files need to be post compiled , Which files need to be recompiled , Even more complex functional operations , because Makefile Like a Shell The script is the same , You can also execute commands from the operating system .

1、Makefile Regular format

Want to master makefile, First, we need to understand two concepts ,⼀ Yes ⽬ mark （target）, another ⼀ One is dependence （dependency）.⽬ Mark means ⼲ what , Or luck ⾏ make after ⽣ What is it ,⽽ Dependence is telling make How to do it to achieve ⽬ mark . stay Makefile in ,⽬ Targets and dependencies are through rules （rule） To express the .

 The goal is XX1: Dependency file 
<TAB> command 1
<TAB> command 2
 
 The goal is XX2: Dependency file 
<TAB> command 1
<TAB> command 2
 
... ...
 
 Instructions 1：
     command 1
     command 2
 Instructions 2：
     command 1
     command 2
... ...

Example ：

Tag：a.o b.o c.o
    gcc -o Tag a.o b.o c.o
a.o: a.c
    gcc -c a.c
b.o: b.c
    gcc -c b.c
c.o: c.c
 
clean:
    rm .o
    rm Tag

2、 Rule description

Makefile Describes the rules of file compilation , Its rules are mainly composed of two parts , They are dependency relations and commands executed , Its structure is as follows ：

targets: prerequisites
	[Tab]command

The instructions are as follows ：

• targets： The goal of the rules , It can be Object File（ It's called an intermediate file ）, It can also be an executable file , It can also be a label ;

• prerequisites： It's our dependency file , To generate targets The required files or targets . It can be more than one , It can also be No ;

• command：make Commands that need to be executed （ Any of the shell command ）. There can be multiple commands , Each command takes one line .

Be careful ： We should use colon to separate our target and dependent files , The beginning of the command must use Tab key .

Let's use the following example Makefile The rules of ,Makefile The code added to the file is as follows ：

test:test.c
    gcc -o test test.c

The function of the above code is to compile test.c file , Through this example, we can explain in detail Makefile The specific use of . among test Yes, the target file , It's also our final executable .

Dependent files are test.c Source file , What you need to do to rebuild the target file is gcc -o test test.c. This is it. Makefile The use of basic grammatical rules of . Use Makefile The way ： First, you need to write Makefile file , And then in shell In the implementation of make command , The program will execute automatically , Get the final target file .

3、C File compilation process

-E ： Preprocessing --> take .h .c Expand to form a file , And generate .i file ;

gcc  -E hello.c -o hello.i

-S ： compile --> The pretreated .i Compile the file into an assembly file .s;

gcc -S hello.i -o hello.s

-c ： assembly --> Will be compiled .s Files are compiled into machine language .o;

gcc -c hello.s -o hello.o

-o ： machine language --> The functions in the object file 、 Variables, etc ;

gcc hello.o -o hello

File format change process ：

.c --> .i -->.s --> .o -->  The goal is 

4、 Use of pseudo targets

.PHONY yes Makefile Keywords of the file , Indicates that the targets in the list behind it are all pseudo targets .

Generally, pseudo targets are used to write cleanup statements , For example, the following statement ：

.PHONY:clean
clean:
	rm -rf hello main.c func1.o func2.o

because , We don't generate clean This file . Fake target It's not a document , It's just a label , because “ Fake target ” It's not a document , therefore make Unable to generate its dependencies and determine whether it will execute . We can only indicate this by showing The goal is To make it work . Of course , Fake target The name of cannot be the same as the file name , Otherwise, it will lose Fake target That's the meaning of .

5、 many .c Of documents Makefile

For example, there are files ：a.cb.cd.ce.c Need to finally get main

Then the code writing format is as follows ：

main:a.o b.o d.o e.o
	gcc a.o b.o d.o e.o -o main
a.o:a.c
	gcc -c a.c -o a.o 
b.o:b.c
	gcc -c b.c -o b.o
d.o:d.c
	gcc -c d.c -o d.o
e.o:e.c
	gcc -c e.c -o e.o

6、 Use of variables

These are commonly used predefined variables .

$* Target file name without extension .

$+ All dependent files , Separate... By spaces , And in the order of emergence , May contain duplicate dependency files .

$< The name of the first dependency file .

$? All dependent files , Separate... By spaces , The modification date of these dependent files is later than the creation date of the target .

[email protected] The full name of the target .

$^ All dependent files , Separate... By spaces , Does not contain duplicate dependency files .
$% If the target is an archive member , Then the variable represents the archive member name of the target .

One of the most common is [email protected]$^ these two items. , We modify the above code with variables as follows ：

TAR =main
OBJ = main.o a.o b.o c.o
CC := gcc
RMRF := rm -rf

$(TAR):$(OBJ)
	$(CC) $^ -o [email protected]

%.o:%.c
	$(CC) -c $^ -o [email protected]

# This sentence can replace all statements in the same format ;
.PHONY:
clear:
	$(RMRF) $(OBJ)

among TAR =mainOBJ = main.o a.o b.o c.oCC := gccRMRF := rm -rf For custom variables , Other zones $ The of the symbol is the system predefined variable .

7、 The rules are obscure

More complicated Makefile We can't write one by one , Then the obscure rules show his power , Let's take a look at the specific use of obscure rules .

According to the above structure description , We are right. Makefile Rewriting layer by layer , The first is the obscure rule , Tell you one of the usages ：

TAR =main
OBJ = main.o a.o b.o c.o
CC := gcc
RMRF := rm -rf

$(TAR):$(OBJ)
	$(CC) $^ -o [email protected]

%.o:%.c
	$(CC) -c $^ -o [email protected]

# This sentence can replace all statements in the same format ;
.PHONY:
clear:
	$(RMRF) $(OBJ)

The following sentences are the writing of obscure rules , We can use these words instead of hundreds of lines of code .

%.o:%.c
	$(CC) -c $^ -o [email protected]

This obscure rule actually tells us , The suffix is .c How to compile the file into .o, The suffix is c How to compile the file into .o.

So far Makefile There are already models and samples ！, Now let's share the specific code execution process ：

8、 At the end

Last , Add a few points to write Makefile Precautions for

1. tab Separate , You can't use spaces .

2.  Every makefile It's better to add one all

3.  With notes “#” Symbol 

4.  The document indicates , Quote other makefile file 

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