Teach you how to transplant tinyriscv to FPGA

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One 、 Download the source code

tinyriscv Official library link ：https://gitee.com/liangkangnan/tinyriscv

So here's what I chose master v2.4 edition : https://gitee.com/liangkangnan/tinyriscv/tree/v2.4/

use Git Clone locally .（ The terminal software used is Cygwin, Installation tutorial ：https://blog.csdn.net/qq_44447544/article/details/123246995?spm=1001.2014.3001.5501）

Two 、 establish Vivado engineering

open tinyriscv Folder , You can see that there are many directories ：

here rtl by tinyriscv Verilog Source code .

use Vivado Create a project , And add the source code and constraints , The specific steps can be seen in tinyriscv\fpga\README.md file , It's very detailed .

3、 ... and 、 Modify the constraint file
The so-called migration is actually to write the correct pin constraint file according to the board you use , And modify the source code according to the requirements .
The basic steps are as follows ：

First modify the binding of the clock and reset pin in the constraint file
Modify the status indication signal pin binding
In the source code ,over、succ、halted_ind It's all status indication signals , Should be bound to the development board LED On , And different development boards LED The way of circuit connection is also different , Some are on for high level , Some are on for low level . and tinyriscv The source code is for low level , That is, when the status indication signal is valid, it is low level , And the Da Vinci development board LED To turn on the high level , So we need to modify the source code , Just remove it upside down .

3. Modify serial port tx and rx Signal pin binding

notes ： This is any pin not used in the development board , Instead of binding the existing serial port on the development board .

4. modify GPIO Pin constraints used by peripherals

5. modify JTAG Pin constraints used

notes ： This is any pin not used in the development board , Not tied FPGA Their own JTAG,FPGA Their own JTAG Already with the development board Flash Bound , Can't use , Like a button ,led The lamp is bound to the same pin , Have been used , Cannot be reused .

6. modify SPI Pin constraints used

7. Add clock constraint 

 because  jtag_TCK  The signal is used as a synchronous clock in the design , There is no signal corresponding to the crystal oscillator clock in the sensitive list . So add the following statement ;

create_clock -name jtag_clk_pin -period 300 [get_ports {jtag_TCK}];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK]

Complete constraint file ：

#  Clock constraint 50MHz, Duty cycle 50%
create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports {clk}];

#  Clock pin 
set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports {clk}]; 

#  Reset pin 
set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {rst}]; 

#  The program execution completion indication pin ,over  by 1 Effective when , Lighten up led0
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {over}]; 

#  Program execution success indication pin ,succ  by 1 Effective when , Lighten up led1
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {succ}]; 

# CPU Stop the indicating pin ,halted_ind  by 1 Effective when , Lighten up led2
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {halted_ind}]; 

#  Serial port download enable pin , Because there is no dial switch and self-locking switch , So bind to key0 On ,key0 Press and hold to enable serial port download 
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {uart_debug_pin}]; 

#  Serial port sending pin 
set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports {uart_tx_pin}]; 

#  Serial port receiving pin 
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {uart_rx_pin}]; 

# GPIO0 Pin 
set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports {gpio[0]}]; 

# GPIO1 Pin 
set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports {gpio[1]}]; 

# JTAG TCK Pin   PortA 0
set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports {jtag_TCK}]; 

create_clock -name jtag_clk_pin -period 300 [get_ports {jtag_TCK}];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK]


# JTAG TMS Pin  PortA 3
set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports jtag_TMS]; 

# JTAG TDI Pin  PortA 1
set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports {jtag_TDI}]; 

# JTAG TDO Pin  PortA 2
set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports jtag_TDO]; 

# SPI MISO Pin 
set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports {spi_miso}]; 

# SPI MOSI Pin 
set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports {spi_mosi}]; 

# SPI SS Pin 
set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports {spi_ss}]; 

# SPI CLK Pin 
set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports {spi_clk}]; 

#SPI  Related settings 
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Four 、 Comprehensive realization
Layout:

resource consumption ;

So as long as the resources on the board are enough , Can be successfully transplanted tinyriscv.

5、 ... and 、 adopt JTAG debug RISCV
Debugger chip ：ftdi4232HL
The configuration file ：
ft4232h.cfg:

adapter driver ftdi
# VID and PID 
ftdi vid_pid 0x0403 0x6011
transport select jtag
# TCK frequency
adapter speed 100

# ftdi_layout_init [data] [direction]
#  Appoint FTDI GPIO The initial data and direction of ,16bit Data width .
#  Parameters data in 1 High level ,0 Indicates low level , And the parameters direction in 1 Indicative output ,0 Indicates input （ Note that this is different from the normal setting ）
ftdi layout_init 0x0018 0x05fb

# ftdi_layout_signal name [-data|-ndata data_mask] [-input|-ninput input_mask] [-oe|-noe oe_mask] [-alias|-nalias name]
#  Create a name for name The signal of .
# [-data|-ndata data_mask] 
# data_mask:pin mask ndata:invert -data:normal bit
# data_mask It's corresponding to pin The mask of the foot ,-ndata Indicates that the input data is reversed ,-data The reverse is not true .
 
ftdi layout_signal nSRST -data 0x0010 -noe 0x0400

tinyriscv.cfg:

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6f

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_reset_timeout_sec 1

init
halt

open cmd Carry out orders ：openocd -f ft4232h.cfg -f tinyriscv.cfg

Successfully detected RISCV CPU.

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