SOC_ SD_ CLK

1. Interface

input       in_TestMode;
input       hclk;
input       hrst_n;
input [7:0] in_clk_divider;      // Frequency division counting 
input       in_sd_clk_enable;	 // Clock enable 
input       hw_stop_clk;         // suffer DMA And read / write control 
output      fifo_sd_clk;		 
output reg  out_sd_clk_o;

2. Internal signals

reg [7:0]   div_counter;   // Frequency division counter 
wire        divider_0_val;
wire        out_sd_clk_tp;
wire        clk_ena_stop;

3. Function code

• Whether to divide frequency ：in_clk_divider by 0 Time and frequency are not divided

assign  divider_0_val = (in_clk_divider == 8'b0 );

• Clock switch

assign  clk_ena_stop  = (!in_sd_clk_enable || hw_stop_clk);

• When frequency division is not required ,out_sd_clk Setting zero can reduce power consumption

[email protected](posedge hclk or negedge hrst_n) begin
    if(!hrst_n)
        out_sd_clk <= 1'b0;
    else if (clk_ena_stop || divider_0_val)
        out_sd_clk <= 1'b0;
    else if (div_counter == in_clk_divider-1)
        out_sd_clk <= ~out_sd_clk;
end

[email protected](posedge hclk or negedge hrst_n) begin
    if(!hrst_n)
        div_counter <= 8'b0;
    else if ( clk_ena_stop || div_0_val)
        div_counter <= 8'b0;
    else begin
        if(div_counter == in_clk_divider-1)
            div_counter <= 8'b0;
        else
            div_counter <= div_counter + 1;
    end
end

• MUX Selection circuit
  

MX2X2 U1
( 
    .Y(fifo_sd_clk),
    .A(out_sd_clk),     //0 
    .B(hclk ),          //1
    .S0 (divider_0_val)
);

TLATNTSCAX4 U2
(
    .ECK(out_sd_clk_tp),   //out
    .SE(1 'b0),            //1
    .E( !clk_ena_stop),    //s
    .CK(fifo_sd_clk )      //0 
);

MX2X2 U3
(
    .Y(out_sd_clk_dft),
    .A(out_sd_clk_tp ), //0
    .B(hclk ),          //1
    .S(in_TestMode)
);