Force/release learning arrangement in IC Verification (5) research on the influence of reg type signals

The previous section , We learned how to view force The signal , And how based on UVM The signal is tested under the platform force operation . today , Let's study it carefully ,force The signal is right RTL In the code reg The influence of type signal .

        Look at the example ： In the following example ,clk,rst ,counter Three signals , Are declared as reg Type variable . Let's focus on counter[7:0] The signal , The signal 8bit, It's a counter .

`timescale 1ns/1ps
import uvm_pkg::*;
//`include "uvm_pkg.sv"
//`include "uvm_macros.svh"
module tb_top();

reg clk,rst;

reg [7:0] counter;

initial begin
clk = 0; 
forever #5 clk = ~ clk;
end

initial begin
rst = 1;
#30 rst = 0 ; 
#25 rst = 1;

end

always @ (posedge clk or negedge rst) begin
  if(!rst) 
     counter <= 8'b0;
  else
     counter <= counter +1;
end

initial begin
run_test("helloworld_test") ;
end

initial begin
$fsdbDumpfile("tb_top.fsdb");
$fsdbDumpvars(0,"tb_top");
end
endmodule

        UVM Code in the platform ：

`ifndef HELLOWORLD_TEST
`define HELLOWORLD_TEST