SOC Clock configuration

1 Working principle of PLL

Soc Of Clock generating unit （CGU） Through external input clock and internal phase-locked loop （PLL） And the frequency division selection logic generates clocks for different frequencies in the chip . The on-chip clock frequency is changed through configuration AHB Bus global control module unit internal PLL register implementation .

CGU The unit contains three phase locked loops , Generate system master clock respectively 、DDR Physical layer clock 、 Ethernet physical layer clock , Its configuration register is located in AHB Bus global control module .CGU The module also generates 1553 Module clock and UART The clock .

The PLL adopts 65nm In the process library PLLSM65LLFRAC PLL , Its maximum output frequency is 1.6GHz, Including decimal configuration mode and integer configuration mode , The PLL in the clock management unit adopts integer configuration mode , User configurable pins are shown in table 1 listed .

surface 1 Common PLL can be configured with pins

Pin name	Direction	A wide	explain
REFDIV（ Frequency divider ）	I	6	PLL frequency division coefficient
FBDIV（ Frequency multiplier ）	I	12	PLL frequency doubling coefficient

Phase locked loop clock FOUTVCO Express , Crystal oscillator input clock CLKIN Express , Frequency multiplier coefficient is FBDIV Express , The frequency divider coefficient is REFDIV Express , The master clock uses MAINPLL Express ,DDR3 For clock DDRPLL Express , Ethernet clock ENETPLL Express . The PLL configuration formula is as follows ：

PLL clock ：FOUTVCO = CLKIN * FBDIV / REFDIV;

Master clock ：MAINPLL = CLKIN * FBDIV / (2*REFDIV);

DDR3 The clock ：DDRPLL = CLKIN * FBDIV / (2*REFDIV);

Ethernet clock ：ENETPLL = CLKIN * FBDIV / (6*REFDIV);

What to pay attention to ： The range of output clock is 400MHz ≤ FOUTVCO ≤ 1600MHz; For configuration signals REFDIV、FBDIV The requirements of ：1 ≤ REFDIV ≤ 63;16 ≤ FBDIV ≤ 1600; Check the PLL status register to know whether the PLL is locked , At this time, configure the PLL .

2 The configuration process

Configuration of main PLL ：

The master PLL generates the system master clock , The principle analysis of the master clock phase locked loop shows that it meets ：

MAINPLL = CLKIN * FBDIV / (2*REFDIV).

Configuration steps ：

1. Read the master PLL register of the global control module , Check the PLL status register LOCK Bit information (0x40c00008 The first of the registers 21 position ), Until the bit is read as 0x1;
2. To the master PLL register BYPASS Bit writing 0x1 operation (0x40c00008 The first of the registers 20 position ), To the master PLL register LOCK Bit writing 0x1 operation （0x40c00008 The first of the registers 21 position ）;
3. Configure the master clock frequency multiplication coefficient of the master PLL register （FBDIV） And the frequency division coefficient of the master clock （REFDIV）,MAINPLL = CLKIN * FBDIV / (2*REFDIV), Configure the main frequency as 400MHz, be FBDIV = 0xA0,REFDIV = 0x5（FBDIV For the register 19-8 position ,REFDIV For the register 5-0 position ）;
4. Wait for the main PLL register frequency latch to complete , Read by loop LOCK You know , If LOCK Bit read as 0, Indicates that the frequency latch is completed ;
5. To the master PLL register BYPASS Bit write 0, Indicates that the clock is in PLL mode , Non bypass mode .

DDR PLL configuration ：

DDR PLL generation system DDR3 The clock , about DDR The principle analysis of PLL shows that it meets ：

DDRPLL = CLKIN * FBDIV / (2*REFDIV).

Configuration steps ：

1. Read out the global control module DDR PLL register , Check the PLL status register LOCK Bit information (0x40c0000c The first of the registers 21 position ), Until the bit is read as 0x1;
2. Yes DDR PLL register BYPASS Bit writing 0x1 operation (0x40c0000c The first of the registers 20 position ), To the master PLL register LOCK Bit writing 0x1 operation （0x40c0000c The first of the registers 21 position ）;
3. To configure DDR PLL register DDR Clock frequency multiplication coefficient （FBDIV） and DDR Clock frequency division coefficient （REFDIV）,DDRPLL = CLKIN * FBDIV / (2*REFDIV), Configure the main frequency as 533MHz, be FBDIV = 0x215,REFDIV = 0x32（FBDIV For the register 19-8 position ,REFDIV For the register 5-0 position ）;
4. wait for DDR PLL register frequency latch complete , Read by loop LOCK You know , If LOCK Bit read as 0, Indicates that the frequency latch is completed ;
5. towards DDR PLL register BYPASS Bit write 0, Indicates that the clock is in PLL mode , Non bypass mode .

3 Data structure encapsulation

According to the distribution of the clock module register address in the memory allocation diagram , Define its address as an integer macro definition , The register is defined as the structural union of each functional bit field . In this way, the integer address is converted to the structural union pointer of the register , You can write the underlying driver through the register bit field , chart 1 Represents the definition and type conversion of the macro definition register , chart 2 Represents the register structure union definition .

 

chart 1

 

chart 2