[Verilog] HDLBits Problem Solution - Verification: Writing Testbenches

Clock

题目链接

module top_module ( );
	reg clk;
    initial begin
       	clk = 0;
        forever #5 clk = ~clk;
    end
    
    dut dut_inst(.clk(clk)) ;
endmodule

Testbench1

题目链接

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
		A = 0;
        B = 0;
        #10 
        A = 1;
        #5
        B = 1;
        #5
        A = 0;
        #20
        B = 0;
    end

endmodule

AND gate

题目链接

module top_module();
    reg [1:0] in;
    wire out;
    initial begin
        in = 'b0;
        #10;
        in = 'b01;
        #10;
        in = 'b10;
        #10;
        in = 'b11;
        #10;
        //$finish;
    end
    
    andgate andgate_inst (
        .in(in),
        .out(out)
    );
endmodule

Testbench2

题目链接

module top_module();
	reg clk;
    reg in;
    reg [2:0] s;
    reg [5:0] STAT;
    wire out;
    initial begin
        STAT = 0;
        clk = 0;
        in = 0;
        s = 'h2;
        forever #5 clk = ~clk;
    end
    
    always @ (negedge clk) begin
        case (STAT)
            0: begin
                s <= 'h6;
            end
            1: begin
                s <= 'h2;
                in <= 1;
            end
            2: begin
                s <= 'h7;
                in <= 0;
            end
            3: begin
                s <= 'h0;
                in <= 1;
            end
            6: begin
                s <= 'h0;
                in <= 0;
            end
            default: begin
            end
        endcase
        
        if (STAT < 6) begin
            STAT <= STAT + 1;
        end
        
    end
    
    q7 q7_inst(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)
    );
endmodule

T flip-flop

题目链接

module top_module ();
	reg clk, reset, t;
    reg [5:0] STAT;
    wire q;
    
    initial begin
        clk = 0;
        reset = 0;
        t = 0;
        STAT = 0;
        forever #1 clk = ~clk;
    end
    
    always @ (posedge clk) begin
        case (STAT)
            0: begin
                reset <= 1;
                STAT <= 1;
            end
            1: begin
                reset <= 0; 
                t <= 1;
                STAT <= 2;
            end
            2: begin
                t <= 0;
            end
        endcase
    end
    
    tff tff_inst(
        .clk(clk),
        .reset(reset),   // active-high synchronous reset
        .t(t),       // toggle
        .q(q)
    );
endmodule