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Cubemx DMA notes
2022-07-02 04:56:00 【@Residual dream】
The timer is on DMA:
About DMA Initial code ：
static void TIM1_CH4_DMA2_TransferComplete_Callback(DMA_HandleTypeDef *hdma)
{
//printf("TIM1_CH4_DMA2_TransferComplete_Callback\r\n");
//_LED_TURN;
}
uint32_t gpiosta[2] = {
0xFFFF0000,0x0000FFFF};
void TIM1_DMA2_Init(void)
{
HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
HAL_NVIC_DisableIRQ(DMA2_Stream5_IRQn);
HAL_NVIC_DisableIRQ(DMA2_Stream1_IRQn);// Disable interrupting updates
#if 0//TIM1_UP Of DMA
htim1.hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM1_CH1_DMA2_TransferComplete_Callback;
HAL_DMA_Start_IT(&hdma_tim1_up,(uint32_t)(&gpiosta[0]), (uint32_t)(&(GPIOC->BSRR)),2);//(uint32_t)(&(GPIOC->BSRR))
__HAL_TIM_ENABLE_DMA(&htim1, TIM_DMA_UPDATE);
#else//TIM1_CH1 + TIM1_CH4 Of DMA
htim1.hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM1_CH1_DMA2_TransferComplete_Callback;
HAL_DMA_Start_IT(&hdma_tim1_ch1,(uint32_t)(&gpiosta[0]), (uint32_t)(&(GPIOB->BSRR)),2);
__HAL_TIM_ENABLE_DMA(&htim1, TIM_DMA_CC1);
htim1.hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM1_CH4_DMA2_TransferComplete_Callback;// Transfer complete callback function
HAL_DMA_Start_IT(&hdma_tim1_ch4_trig_com,(uint32_t)(&gpiosta[0]), (uint32_t)(&(GPIOC->BSRR)),2);// take gpiosta Data moved to GPIOC->BSRR
__HAL_TIM_ENABLE_DMA(&htim1, TIM_DMA_CC4);// Enable timer update DMA request
#endif
}
The main function starts ：
HAL_TIM_PWM_Start(&htim1,TIM_CHANNEL_1);
HAL_TIM_PWM_Start(&htim1,TIM_CHANNEL_4);
TIM1_DMA2_Init();
while(1)
{
HAL_Delay(3000);
}
About tim.c All the code ：
/** ****************************************************************************** * @file tim.c * @brief This file provides code for the configuration * of the TIM instances. ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2022 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */
/* Includes ------------------------------------------------------------------*/
#include "tim.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
TIM_HandleTypeDef htim1;
DMA_HandleTypeDef hdma_tim1_ch1;
DMA_HandleTypeDef hdma_tim1_ch4_trig_com;
/* TIM1 init function */
void MX_TIM1_Init(void)
{
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {
0};
TIM_MasterConfigTypeDef sMasterConfig = {
0};
TIM_OC_InitTypeDef sConfigOC = {
0};
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {
0};
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
htim1.Init.Prescaler = 1-1;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 168/2-1;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = htim1.Init.Period/2;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
{
Error_Handler();
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
sBreakDeadTimeConfig.DeadTime = 0;
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
}
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
if(tim_baseHandle->Instance==TIM1)
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* TIM1 clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
/* TIM1 DMA Init */
/* TIM1_CH1 Init */
hdma_tim1_ch1.Instance = DMA2_Stream1;
hdma_tim1_ch1.Init.Channel = DMA_CHANNEL_6;
hdma_tim1_ch1.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_tim1_ch1.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_tim1_ch1.Init.MemInc = DMA_MINC_ENABLE;
hdma_tim1_ch1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_tim1_ch1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_tim1_ch1.Init.Mode = DMA_CIRCULAR;
hdma_tim1_ch1.Init.Priority = DMA_PRIORITY_VERY_HIGH;
hdma_tim1_ch1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_tim1_ch1) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(tim_baseHandle,hdma[TIM_DMA_ID_CC1],hdma_tim1_ch1);
/* TIM1_CH4_TRIG_COM Init */
hdma_tim1_ch4_trig_com.Instance = DMA2_Stream4;
hdma_tim1_ch4_trig_com.Init.Channel = DMA_CHANNEL_6;
hdma_tim1_ch4_trig_com.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_tim1_ch4_trig_com.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_tim1_ch4_trig_com.Init.MemInc = DMA_MINC_ENABLE;
hdma_tim1_ch4_trig_com.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_tim1_ch4_trig_com.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_tim1_ch4_trig_com.Init.Mode = DMA_CIRCULAR;
hdma_tim1_ch4_trig_com.Init.Priority = DMA_PRIORITY_VERY_HIGH;
hdma_tim1_ch4_trig_com.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_tim1_ch4_trig_com) != HAL_OK)
{
Error_Handler();
}
/* Several peripheral DMA handle pointers point to the same DMA handle. Be aware that there is only one stream to perform all the requested DMAs. */
__HAL_LINKDMA(tim_baseHandle,hdma[TIM_DMA_ID_CC4],hdma_tim1_ch4_trig_com);
__HAL_LINKDMA(tim_baseHandle,hdma[TIM_DMA_ID_TRIGGER],hdma_tim1_ch4_trig_com);
__HAL_LINKDMA(tim_baseHandle,hdma[TIM_DMA_ID_COMMUTATION],hdma_tim1_ch4_trig_com);
/* USER CODE BEGIN TIM1_MspInit 1 */
/* USER CODE END TIM1_MspInit 1 */
}
}
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {
0};
if(timHandle->Instance==TIM1)
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
/**TIM1 GPIO Configuration PA8 ------> TIM1_CH1 PA11 ------> TIM1_CH4 */
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
{
if(tim_baseHandle->Instance==TIM1)
{
/* USER CODE BEGIN TIM1_MspDeInit 0 */
/* USER CODE END TIM1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM1_CLK_DISABLE();
/* TIM1 DMA DeInit */
HAL_DMA_DeInit(tim_baseHandle->hdma[TIM_DMA_ID_CC1]);
HAL_DMA_DeInit(tim_baseHandle->hdma[TIM_DMA_ID_CC4]);
HAL_DMA_DeInit(tim_baseHandle->hdma[TIM_DMA_ID_TRIGGER]);
HAL_DMA_DeInit(tim_baseHandle->hdma[TIM_DMA_ID_COMMUTATION]);
/* USER CODE BEGIN TIM1_MspDeInit 1 */
/* USER CODE END TIM1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
if(htim->Instance == TIM1)
{
//_LED_TURN;
//printf("HAL_TIM_PeriodElapsedCallback\r\n");
}
}
static void TIM1_CH1_DMA2_TransferComplete_Callback(DMA_HandleTypeDef *hdma)
{
//printf("TIM1_CH1_DMA2_TransferComplete_Callback\r\n");
//_LED_TURN;
}
static void TIM1_CH4_DMA2_TransferComplete_Callback(DMA_HandleTypeDef *hdma)
{
//printf("TIM1_CH4_DMA2_TransferComplete_Callback\r\n");
//_LED_TURN;
}
uint32_t gpiosta[2] = {
0xFFFF0000,0x0000FFFF};
void TIM1_DMA2_Init(void)
{
HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
HAL_NVIC_DisableIRQ(DMA2_Stream5_IRQn);
HAL_NVIC_DisableIRQ(DMA2_Stream1_IRQn);// Disable interrupting updates
#if 0//TIM1_UP Of DMA
htim1.hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM1_CH1_DMA2_TransferComplete_Callback;
HAL_DMA_Start_IT(&hdma_tim1_up,(uint32_t)(&gpiosta[0]), (uint32_t)(&(GPIOC->BSRR)),2);//(uint32_t)(&(GPIOC->BSRR))
__HAL_TIM_ENABLE_DMA(&htim1, TIM_DMA_UPDATE);
#else//TIM1_CH1 + TIM1_CH4 Of DMA
htim1.hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM1_CH1_DMA2_TransferComplete_Callback;
HAL_DMA_Start_IT(&hdma_tim1_ch1,(uint32_t)(&gpiosta[0]), (uint32_t)(&(GPIOB->BSRR)),2);
__HAL_TIM_ENABLE_DMA(&htim1, TIM_DMA_CC1);
htim1.hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM1_CH4_DMA2_TransferComplete_Callback;// Transfer complete callback function
HAL_DMA_Start_IT(&hdma_tim1_ch4_trig_com,(uint32_t)(&gpiosta[0]), (uint32_t)(&(GPIOC->BSRR)),2);// take gpiosta Data moved to GPIOC->BSRR
__HAL_TIM_ENABLE_DMA(&htim1, TIM_DMA_CC4);// Enable timer update DMA request
#endif
}
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
About DMA The peripheral address used must meet DMA Transmission restrictions for ： Compared with DMA1 Can't visit AHB1 Peripheral , That is, for example, not DMA1 Move GPIOC\GPIOB And other peripheral data transmission 
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