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AHB_ Bus_ Matrix_ 3x3 design

2022-06-11 19:39:00 【Starry and】

Catalog

1. Function description
2. framework
3. logic design

1. Function description

When more than one AHB master With many AHB slave When communicating , You can use a AHB Agreed bus matrix Realize interconnection .

for example

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2. framework

According to the previous description , One master multi slave system needs decoder Yes Master Of HADDR To decode different Slave Make a selection , meanwhile Slave The read data also needs MUX Return to according to the film selection result Master. here bus matrix Design will decoder And MUX Merge into decoder, And for each Master Match one decoder.

For each of these Slave Come on , There may be more than one at the same time Master Visit it , Therefore need arbiter Implement arbitration , Therefore, tentative bus matrix The architecture of is as follows ：

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2.1. ahb_bus_matrix_3x3

The interface is as follows

Group	Signal	Direction	Width(bits)	Description
	HCLK	input	1	The clock
	HRSTn	input	1	Reset , Low efficiency
MST_IO0	HADDR_mst0	input	HADDR_WIDTH	AHB Write the address
	HBURST_mst0	input	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_mst0	input	3	Determines the bit width of the transmitted data
	HTRANS_mst0	input	2	Transmission status
	HWDATA_mst0	input	HDATA_WIDTH	AHB Writing data
	HWRITE_mst0	input	1	Gao Weiwen , Low for reading
	HRDATA_mst0	output	HDATA_WIDTH	AHB Reading data
	HREADY_mst0	output	1	Master Received from Slave Effective signal
MST_IO1	HADDR_mst1	input	HADDR_WIDTH	AHB Write the address
	HBURST_mst1	input	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_mst1	input	3	Determines the bit width of the transmitted data
	HTRANS_mst1	input	2	Transmission status
	HWDATA_mst1	input	HDATA_WIDTH	AHB Writing data
	HWRITE_mst1	input	1	Gao Weiwen , Low for reading
	HRDATA_mst1	output	HDATA_WIDTH	AHB Reading data
	HREADY_mst1	output	1	Master Received from Slave Effective signal
MST_IO2	HADDR_mst2	input	HADDR_WIDTH	AHB Write the address
	HBURST_mst2	input	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_mst2	input	3	Determines the bit width of the transmitted data
	HTRANS_mst2	input	2	Transmission status
	HWDATA_mst2	input	HDATA_WIDTH	AHB Writing data
	HWRITE_mst2	input	1	Gao Weiwen , Low for reading
	HRDATA_mst2	output	HDATA_WIDTH	AHB Reading data
	HREADY_mst2	output	1	Master Received from Slave Effective signal

Group	Signal	Direction	Width(bits)	Description
SLV_IO0	HADDR_slv0	output	HADDR_WIDTH	AHB Write the address
	HSEL_slv0	input	1	Chip selection
	HBURST_slv0	output	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_slv0	output	3	Determines the bit width of the transmitted data
	HTRANS_slv0	output	2	Transmission status
	HWDATA_slv0	output	HDATA_WIDTH	AHB Writing data
	HWRITE_slv0	output	1	Gao Weiwen , Low for reading
	HRDATA_slv0	input	HDATA_WIDTH	AHB Reading data
	HREADYOUT_slv0	input	1	Slave Prepare the signal
SLV_IO1	HADDR_slv0	output	HADDR_WIDTH	AHB Write the address
	HSEL_slv1	input	1	Chip selection
	HBURST_slv1	output	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_slv1	output	3	Determines the bit width of the transmitted data
	HTRANS_slv1	output	2	Transmission status
	HWDATA_slv1	output	HDATA_WIDTH	AHB Writing data
	HWRITE_slv1	output	1	Gao Weiwen , Low for reading
	HRDATA_slv1	input	HDATA_WIDTH	AHB Reading data
	HREADYOUT_slv1	input	1	Slave Prepare the signal
SLV_IO2	HADDR_slv0	output	HADDR_WIDTH	AHB Write the address
	HSEL_slv2	input	1	Chip selection
	HBURST_slv2	output	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_slv2	output	3	Determines the bit width of the transmitted data
	HTRANS_slv2	output	2	Transmission status
	HWDATA_slv2	output	HDATA_WIDTH	AHB Writing data
	HWRITE_slv2	output	1	Gao Weiwen , Low for reading
	HRDATA_slv2	input	HDATA_WIDTH	AHB Reading data
	HREADYOUT_slv2	input	1	Slave Prepare the signal

Parameter	Units	Description
HADDR_WIDTH	bit	AHB Address width
HDATA_WIDTH	bit	AHB Data width

2.2. decoder

Combine the decoder and sorter into decoder, The following interfaces can be obtained

Group	Signal	Direction	Width(bits)	Description
	HCLK	input	1	The clock
	HRSTn	input	1	Reset , Low efficiency
MST_IO	HADDR	input	HADDR_WIDTH	AHB Write the address
	HRESP	output	1	AHB Transmit feedback
	HRDATA	output	HDATA_WIDTH	from Slave Read out data
	HREADY	output	1	Transmission success flag
SLV_IO0	HSEL_slv0	output	1	Yes AHB Slave0 The movie selection of
	HREADYOUT_slv0	input	1	AHB Slave0 Input preparation signal
	HRESP_slv0	input	1	AHB Slave0 Input feedback signal
	HRDATA_slv0	input	HDATA_WIDTH	AHB Slave0 Input read data signal
SLV_IO1	HSEL_slv1	output	1	Yes AHB Slave1 The movie selection of
	HREADYOUT_slv1	input	1	AHB Slave1 Input preparation signal
	HRESP_slv1	input	1	AHB Slave1 Input feedback signal
	HRDATA_slv1	input	HDATA_WIDTH	AHB Slave1 Input read data signal
SLV_IO2	HSEL_slv2	output	1	Yes AHB Slave2 The movie selection of
	HREADYOUT_slv2	input	1	AHB Slave2 Input preparation signal
	HRESP_slv2	input	1	AHB Slave2 Input feedback signal
	HRDATA_slv2	input	HDATA_WIDTH	AHB Slave2 Input read data signal

Parameter	Units	Description
HADDR_WIDTH	bit	AHB Address width
HDATA_WIDTH	bit	AHB Data width

2.3. arbiter

Here arbiter Is based on multiple AHB Master For this Slave The result of the film selection , Which one will be arbitrated AHB Master With this Slave signal communication , And with the real AHB Slave Interact

But actually aribiter There are many algorithms , This article will implement .

Group	Signal	Direction	Width(bits)	Description
	HCLK	input	1	The clock
	HRSTn	input	1	Reset , Low efficiency
MST_IO0	HADDR_mst0	input	HADDR_WIDTH	AHB Write the address
	HBURST_mst0	input	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_mst0	input	3	Determines the bit width of the transmitted data
	HTRANS_mst0	input	2	Transmission status
	HWDATA_mst0	input	HDATA_WIDTH	AHB Writing data
	HWRITE_mst0	input	1	Gao Weiwen , Low for reading
	HREADY_mst0	input	1	Indicates whether the transmission is correct
	HSEL_mst0	input	1	Said to the Slave Strobe
	HRDATA_mst0	output	HDATA_WIDTH	AHB Reading data
	HREADYOUT_mst0	output	1	Master Received from Slave Effective signal
MST_IO1	HADDR_mst1	input	HADDR_WIDTH	AHB Write the address
	HBURST_mst1	input	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_mst1	input	3	Determines the bit width of the transmitted data
	HTRANS_mst1	input	2	Transmission status
	HWDATA_mst1	input	HDATA_WIDTH	AHB Writing data
	HWRITE_mst1	input	1	Gao Weiwen , Low for reading
	HREADY_mst1	input	1	Indicates whether the transmission is correct
	HSEL_mst1	input	1	Said to the Slave Strobe
	HRDATA_mst1	output	HDATA_WIDTH	AHB Reading data
	HREADYOUT_mst1	output	1	Master Received from Slave Effective signal
MST_IO2	HADDR_mst2	input	HADDR_WIDTH	AHB Write the address
	HBURST_mst2	input	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE_mst2	input	3	Determines the bit width of the transmitted data
	HTRANS_mst2	input	2	Transmission status
	HWDATA_mst2	input	HDATA_WIDTH	AHB Writing data
	HWRITE_mst2	input	1	Gao Weiwen , Low for reading
	HREADY_mst2	input	1	Indicates whether the transmission is correct
	HSEL_mst2	input	1	Said to the Slave Strobe
	HRDATA_mst2	output	HDATA_WIDTH	AHB Reading data
	HREADYOUT_mst2	output	1	Master Received from Slave Effective signal
SLV_IO	HADDR	output	HADDR_WIDTH	AHB Write the address
	HBURST	output	3	AHB burst The number of transmission times and increasing mode during transmission
	HSIZE	output	3	Determines the bit width of the transmitted data
	HTRANS	output	2	Transmission status
	HWDATA	output	HDATA_WIDTH	AHB Writing data
	HWRITE	output	1	Gao Weiwen , Low for reading
	HREADY	output	1	Indicates whether the transmission is correct
	HSEL	output	1	Said to the Slave Strobe
	HRDATA	input	HDATA_WIDTH	AHB Reading data
	HREADYOUT	input	1	come from Slave Effective signal

Parameter	Units	Description
HADDR_WIDTH	bit	AHB Address width
HDATA_WIDTH	bit	AHB Data width

3. logic design

3.1. decoder

decoder The meaning of It's based on Master Of HADDR Information on the corresponding Slave Make a selection , Will be Slave The output signal of is fed back to Master.

module decoder#(
	parameter HADDR_WIDTH	=	8,
	parameter HDATA_WIDTH 	=	16
	)(
	input 					 		hrstn,
	input 					 		hclk,
		
	input 	[HADDR_WIDTH-1:0]		haddr,
	output							hresp,
	output 	[HDATA_WIDTH-1:0]		hrdata,
	output							hready,
	
	output							hsel_slv0,
	input							hreadyout_slv0,
	input							hresp_slv0,
	input 	[HDATA_WIDTH-1:0]		hrdata_slv0,
	
	output							hsel_slv1,
	input							hreadyout_slv1,
	input							hresp_slv1,
	input 	[HDATA_WIDTH-1:0]		hrdata_slv1,
	
	output							hsel_slv2,
	input							hreadyout_slv2,
	input							hresp_slv2,
	input 	[HDATA_WIDTH-1:0]		hrdata_slv2
	);

reg							hresp_r;
reg 	[HDATA_WIDTH-1:0]	hrdata_r;
reg							hready_r;
reg							hsel_slv0_r;
reg							hsel_slv1_r;
reg							hsel_slv2_r;

[email protected](*) begin
	case(haddr[31:16])
		16'h0000:
			hresp_r = hresp_slv0;
		16'h0001:
			hresp_r = hresp_slv1;
		16'h0002:
			hresp_r = hresp_slv2;
		default:
			hresp_r = 1'b0;
	endcase
end

assign hresp = hresp_r;

[email protected](*) begin
	case(haddr[31:16])
		16'h0000:
			hrdata_r = hrdata_slv0;
		16'h0001:
			hrdata_r = hrdata_slv1;
		16'h0002:
			hrdata_r = hrdata_slv2;
		default:
			hrdata_r = 'h0;
	endcase
end

assign hrdata = hrdata_r;

[email protected](*) begin
	case(haddr[31:16])
		16'h0000:
			hready_r = hreadyout_slv0;
		16'h0001:
			hready_r = hreadyout_slv1;
		16'h0002:
			hready_r = hreadyout_slv2;
		default:
			hready_r = 1'b0;
	endcase
end

assign hready = hready_r;

[email protected](*) begin
	case(haddr[31:16])
		16'h0000:
			begin
				hsel_slv0_r = 1'b1;
				hsel_slv1_r = 1'b0;
				hsel_slv2_r = 1'b0;
			end
		16'h0001:
			begin
				hsel_slv0_r = 1'b0;
				hsel_slv1_r = 1'b1;
				hsel_slv2_r = 1'b0;
			end
		16'h0002:
			begin
				hsel_slv0_r = 1'b0;
				hsel_slv1_r = 1'b0;
				hsel_slv2_r = 1'b1;
			end
		default:
			begin
				hsel_slv0_r = 1'b0;
				hsel_slv1_r = 1'b0;
				hsel_slv2_r = 1'b0;
			end
	endcase
end

assign hsel_slv0 = hsel_slv0_r;
assign hsel_slv1 = hsel_slv1_r;
assign hsel_slv2 = hsel_slv2_r;

endmodule