Learn the knowledge you need to know about the communication protocol I2C bus

I2C It was Philips in 80 A serial communication bus designed in the s , Using multiple groups of slave architectures , It is mainly used in the main chip and sensor of the system 、EEPROM And other peripheral equipment components .

I2C All devices on the bus have a master-slave relationship , Support multiple master devices online , It also supports arbitration and conflict detection .

I2C The maximum number of slaves supported by the bus is theoretically 127 individual , Each device has only one unique address , So that the main equipment can select the corresponding equipment for communication .

I2C The agreement only needs SCL and SDA Two lines .

SCL Is the abbreviation of serial clock line , The synchronization clock is generated by the master device , Responsible for transmitting clock signals .

SDA Is the abbreviation of serial data line , Used to transmit data signals .

Since both data lines are open drain output , Therefore, it is necessary to connect the pull-up resistor during communication . Usually in standard mode 100KBPS Use 10K The pull-up resistance of , In fast mode 400KBPS Use 2K The pull-up resistance of .I2C The bus also has high-speed mode 3.4MBPS And ultra fast mode 5MBPS You can choose .

When the main equipment and heavy equipment transmit data, they need to follow the corresponding data structure sequence .

The first part is the start signal , After the master sends the start condition signal , All slaves, even in sleep mode, will become active and wait to receive address bits .

The second part is address bits and read-write bits , Usually the address bits occupy seven bits of data , The master device needs to send the corresponding slave address , Match the slave attached to the bus .I2C It also supports ten bit addressing , The read / write bit has specified the transmission direction of the data .

The third part is the reply bit , Every time the host sends data, it will wait for the response signal from the slave device ACK.

The fourth part is the address of the internal register or the instruction data of the slave device .

The fifth part is the data block sent .

Finally, the stop bit .

Next, let's take a look at the timing table I2C agreement , The condition for starting the signal is SCL When it's high level ,SDA Jump from high level to low level , After that ,SDA Start with SCL Clock sending device address data ,8bit The data of contains seven bit device address data and degree reading data .

For read and write bits , If the master device sends to the slave device 0, If it is sent from the slave device to the master device in turn, it is 1, Then comes the reply bit , This data is in the 9 Clock signal cycle expression .

If the response signal is sent from the device ACK, that SDA Will be pulled down , If there is no answer signal , It means that the previous address data has not been received from the device ,SDA Will output to high level .

cause NACK There are many reasons , For example, the master device sends the wrong address data , Or the slave device is busy and cannot answer , The corresponding master device will choose to resend or stop according to the corresponding situation .

If the master device receives the reply signal , The address information of the internal register of the same device will be sent , For example, we want to read ADSL345 Acceleration sensor X Axis of the data ,ADSL The device address of is 0x53,X The internal register address of the axis data is 0x32, The corresponding master device needs to access after pairing the slave device address ADSL Internal address 0x32 In order to read X Axis data information .

After each transmission, a reply bit will follow , If the receiver successfully receives data , Is set to 0, Otherwise keep the logic 1, Then the eight bit data frame and the corresponding response are , The end is , The end condition is SCL When it's high level ,SD A It will jump from low level to high level .

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