IIC communication protocol for single chip microcomputer

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Concept

I2C(IIC,Inter－Integrated Circuit), Two wire serial bus , from PHILIPS The company developed for connecting microcontrollers and peripherals . It's made up of data lines SDA And the clock SCL The serial bus , Can send and receive data . stay CPU And accused IC Between 、IC And IC Two way transmission between , High speed IIC The bus can reach 400kbps above .

Hardware IIC: Hardware IIC Faster than simulation , And you can use DMA. Hardware IIC It will automatically match the communication sequence with the slave , Just configure the hardware IIC Some functions of . Software IIC: Simulation with software IIC Sequence diagram , So as to communicate with the slave

IIC Transmission characteristics

1. Half duplex ： Half duplex communication allows signals to be transmitted in both directions , However, only one-way signal transmission is allowed on one channel at a certain time , Simplex communication with switchable direction

2. Serial synchronous communication ： The data passes through a SDA Line transmission ,SCL Provide synchronization clock . The biggest feature of synchronous communication is the communication between both sides SCL The clock wires are connected together .

3. Master slave communication ： Each communication cycle is initiated and ended by the master device , The slave only responds passively to the master , I can't do anything by myself . There are master and slave , Support multiple slaves .

4. Transport order ： High in the former , Low in the back

5. Only SDA And SCL Two wires , However, a common ground wire is required between the master and the slave , Otherwise, how can the slave know whether the level sequence sent by the host is high or low ！

6.SDA And SCL The bus must be connected to the pull-up resistor .

7, Transmission rate ：I2C agreement v2.1 Three rates are specified (bps) -100K -400K -3.4M

The communication rate is based on the host SCL Speed to communicate ,SCL The communication speed on the shall be less than the maximum communication speed specified by the master and the slave

The communication process of one master and multiple slaves ： The master device sends the first message in each communication cycle 8 Bit slave address , Actually 8 There is only 7 Bit is the slave device address (datasheet There's a device address ), also 1 Bit indicates whether to write or read from the master device ( Determined by the slave device ) To bus （ The master device is sent in the form of broadcast , As long as all the slave devices on the bus can actually receive this message ）. Then each slave device on the bus can receive this address , After receiving the address, compare it with your own device address to see if it is equal . If it is equal, it means that the main equipment is talking to me this time , If you don't want to wait, this communication has nothing to do with me , Don't listen .

IIC sequential

Idle state ：SDA And SCL The bus is in the high-level state

Start signal timing and end signal timing

Response signal timing

Every byte sent by the transmitter , Just before the clock pulse 9 Release the data line during , A reply signal is fed back by the receiver . The response signal is low (0) when , It is stipulated as effective answer （ACK Abbreviate answer bit ）, Indicates that the receiver has successfully received the byte ; The response signal is high (1) when , Specified as non response bit （NACK）, Generally, it means that the receiver failed to receive the byte .

The validity of the data

SCL During high level ,SDA The data of cannot be transformed ;SCL During low level ,SDA The data can only be transformed .

The read byte and write section sequence of the slave should be written according to the sequence diagram of the slave

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