Learn FPGA from the bottom structure (16) -- customization and testing of pll/mmcm IP

Catalog

Series catalog and portal

1、PLL IP The custom of

①、 first page

②、 The second page  

③、 The third page

④、 Page four

⑤、 Page 5

2、PLL IP Instantiation and testing of

2.1、 Exemplify a PLL IP nucleus

2.2、 To write testbench

2.3、 The simulation test

3、 Summary and reference

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Series catalog and portal

        《 Start with the underlying structure FPGA》 Directory and portal

        Customizing one PLL IP Before nuclear , It is strongly recommended that you read ： Start with the underlying structure FPGA（15）----MMCM And PLL

        In this article , Have been to PLL/MMCM IP The key factors of nuclear are explained in detail .

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1、PLL IP The custom of

        because MMCM Count as PLL A functional superset , The extra dynamic phase shift and spread function are not explained in detail in this chapter , Therefore, the following contents are used PLL IP Kernel Implementation .

1. After creating a new project , Click on IP Catalog
2. It will appear after clicking IP Catalog page , stay IP Search in the search box of the kernel clocking
3. According to the screening , Double click to select PLL nucleus Clocking Wizard

 

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①、 first page

 

① Clock monitoring  

        Enable Clock Monitoring ： Real time monitoring can detect the clock at any time

② Implementation types

        primitive： Can choose PLL still MMCM To achieve , In general PLL Enough to achieve most functions ,MMCM Suitable for more advanced applications , Such as dynamic phase shifting or frequency spreading

③ Clock characteristics

        Frequency Synthesis： Frequency synthesis , Check it to modify the desired clock frequency output

        Phase Alignment： Phase alignment , When checked, the phase of the input signal and the output signal are consistent , The price is an extra one BUFG

        Dynamic Reconfig : Can pass AXI4 The interface is dynamically modified during use IP To configure , Realize more flexible clock output , Specific implementation can refer to ：xapp888_7Series_DynamicRecon

        Safe Clock Starup : Do not output before the clock is stable , Benefits: the clock is more stable and safe , Disadvantages may affect performance

        Minimize Power : Optimize power consumption , The cost is that performance may be affected

④ Clock jitter （Jitter ） Optimize

        Balanced： The default option , performance 、 Power balance state

        Minimize Output Jitter： Minimize output clock jitter , The cost is that the power consumption becomes larger and may lead to phase error

        Maximize Input Jitter filtering： Maximize input clock filtering , Allow the jitter of the input clock signal to increase （ That is to say, the input clock signal with worse quality is allowed ）, However, it may cause the jitter of the output clock signal to become larger

⑤ Dynamic reconfiguration options ： This function is not checked , So don't say

⑥ Input clock information

        Optional input two clock signals as input

        Configure the frequency of the input clock 、 shake 、 source

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②、 The second page  

 

① Output clock information setting

        Check the clock information to be output , Including frequency , Phase relationship and duty cycle , It should be noted that the set value may not be achieved , Everything is subject to the actual value .

        We choose 5 Different types of clock frequencies , See the table for specific information .

② Check the output sequence of different signals , Need to be in the ① Page check Safe Clock Starup Options

③ Clock feedback ： Only in the ① Page checked Phase Alignment Options can be checked

        automatic control on-chip And user-controlled on-chip： If your output clock signal is FPGA For internal use , Then the feedback path is on chip Of , The difference between automatic and user-defined is whether the feedback clock pin is automatically connected or open to the user to connect

        automatic control off-chip And user-controlled off-chip： If your output clock signal is to FPGA Used externally , Then the feedback path is off chip Of , The difference between automatic and user-defined is whether the feedback clock pin is automatically connected or open to the user to connect .automatic control off-chip In mode, it is also necessary to specify that the feedback pin is a single ended signal （single ended） Or differential signal （differential）

④ optional

        reset： Reset signal

        power_down： Power down mode （ close PLL, Stop output ）

        locked： When set, it means PLL The output signal is valid , Usually use PLL Do not use the output clock signal until the signal is valid

⑤ Reset type

        Select high-level reset or low-level reset . Suggested choice xilinx Common high-level reset .

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③、 The third page

        Rename the signal of the output port , Generally, for the sake of generality , Name change is not recommended . 

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④、 Page four

        Direct pair PLL The underlying primitive operates , Realize more detailed customized design . Generally not used .

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⑤、 Page 5

         PLL IP Summary of nuclear design information , Confirm the design information .

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2、PLL IP Instantiation and testing of

2.1、 Exemplify a PLL IP nucleus

        Follow the above steps to generate IP after , Copy IP The instantiation template provided by the core .

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2.2、 To write testbench

        We write directly testbench To exemplify PLL IP Nuclear testing ：

`timescale 1ns / 1ns

module tb_pll();

reg 	clk_in;		// Input clock 50M
reg		reset;		// Highly effective reset signal 

wire 	locked;
wire	clk50_90d;	//50M, The offset 90 degree 
wire	clk50_n90d;	//50M, The offset -90 degree 	
wire	clk50_d75;	//50M, Duty cycle 75%
wire	clk_100;	//100M
wire	clk_150;	//150M	

always #10 clk_in = ~clk_in;	// Generate input clock 

// Initialize the input signal 
initial begin
	reset = 1'b1;
	clk_in  = 1'b0;
	#100
	reset = 1'b0;
	
	wait(locked);		//PLL The output is valid 
	#1000 $finish;
end

// Exemplification PLL IP nucleus 
clk_wiz_0 instance_name
(
	// Clock out ports
	.clk50_90d	(clk50_90d),     // output clk50_90d
	.clk50_n90d	(clk50_n90d),     // output clk50_n90d
	.clk50_d75	(clk50_d75),     // output clk50_d75
	.clk_100	(clk_100),     	// output clk_100
	.clk_150	(clk_150),     	// output clk_150
	// Status and control signals
	.reset		(reset), 		// input reset
	.locked		(locked),       // output locked
	// Clock in ports
	.clk_in1	(clk_in)
);    
  	
endmodule

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2.3、 The simulation test

         Use vivado Built in simulation tools simulator Run the simulation , The simulation results are as follows ： 

        Next, look at each signal separately ：

        （1）clk50_90d：50M, The offset 90 degree

        

        （2）clk50_n90d：50M, The offset -90 degree

 

        （3）clk50_d75：50M, Duty cycle 75%

 

        （4）clk_100：100M

 

        （5）clk_150：150M

 

        You can see , All output clock signals are consistent with the expected design , The simulation is successful .

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3、 Summary and reference

• For general applications ,PLL IP It's very easy to get started ; As for dynamic reconfiguration and dynamic phase shift functions , It may be a little troublesome
• Don't use frequency division clock in ordinary design , Instead, try to use PLL or MMCM To realize the design of clock signal

         Reference material 1：pg065-clk-wiz

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