Verilog grammar basics HDL bits training 05

Preface

Several examples of this time focus on for Circulation and generate&for Loop statement , Benefited greatly

More Verilog Features

One 、Conditional ternary operator

Ternary conditional operators ：((a)?:c:b);? The former is the condition , Conditions will be met c give , If the condition does not hold, it will b give .

• RTL Code

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    // assign intermediate_result1 = compare? true: false;
    wire [7:0]min1;
    wire [7:0]min2;
    
    assign min1 = (a<b) ? a:b;
    assign min2 = (c<d) ? c:d;
    assign min = (min1<min2) ? min1:min2; 

endmodule

• Simulation oscillogram
  

Two 、Reduction operators

Perform bit operations on all bits in a vector

• RTL Code

module top_module (
    input [7:0] in,
    output parity); 

    assign parity = ^ in[7:0];
    
endmodule

3、 ... and 、Reduction:Even wider gates

Conduct 100 All bit operations of bit data

• RTL Code

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    assign out_and = & in[99:0];
    assign out_or = | in[99:0];
    assign out_xor = ^ in[99:0];

endmodule

• Simulation oscillogram

Four 、Combinational for-loop:Vector reversal

Will input 100 Bit data is inverted and assigned to the output

• RTL Code

module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer i;
    always @(*)
        for(i=0;i<=99;i=i+1)
            out[i] = in[99-i];

endmodule

5、 ... and 、Combinational for-loop:255-bit population count

Statistics 255 Bit data ‘1’（ High level ） The number of , And send the total number of statistics to out in

• RTL Code

module top_module( 
    input [254:0] in,
    output [7:0] out );

    integer i;
    always @(*)
    begin
        out = 1'b0;
        for(i=0;i<=254;i=i+1)
            begin
                if(in[i])
                    out = out+1;
               	else
                    out = out;
            end
    end
endmodule

• Simulation oscillogram
  

6、 ... and 、Generate for-loop:100-bit binary adder

To design a 100 Bit full adder ,cin Is the overall carry ,cout[99] Is the final carry , Use generate sentence

• RTL Code

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    genvar i;
    generate 
        for(i=0;i<100;i=i+1)begin:adder
            if(i==0)
                assign {
    cout[0] , sum[0]} = a[0] + b[0] + cin;
            else
                assign {
    cout[i] , sum[i]} = a[i] + b[i] + cout[i-1];
        end
    endgenerate 
    
endmodule 

• Use integer and for sentence

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    integer i;
    always @(*) 
        for(i=0;i<100;i=i+1)
            begin
            if(i==0)
                {
    cout[0] , sum[0]} = a[0] + b[0] + cin;
            else
                {
    cout[i] , sum[i]} = a[i] + b[i] + cout[i-1];
            end
endmodule 

7、 ... and 、Generate for-loop:100-digit BCD adder

To design a BCD Code full adder , call bcd_fadd Instantiation module , because always Instantiated modules cannot be called in blocks , So it can't be used always Block and for The combination of sentences , Only use generate sentence

• RTL Code

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    
    wire [99:0]cout_t;
    genvar i;
    generate
        for(i=0;i<100;i=i+1)begin:bcd_fadd
            if(i==0)
                bcd_fadd bcd_fadd_inst(a[3:0],b[3:0],cin,cout_t[0],sum[3:0]);
            else
                bcd_fadd bcd_fadd_inst(a[4*i+3:4*i],b[4*i+3:4*i],cout_t[i-1],cout_t[i],sum[4*i+3:4*i]);
        end
        assign cout = cout_t[99];
    endgenerate

endmodule