FPGA_ Initial use process of vivado software_ Ultra detailed

It should be noted that ： I'm using the version 2018.2, Different versions of software may differ

Introduction to the development process ： Open software — New project — Design input — Analysis and synthesis — Constraint input — Design implementation — Generate and download bitstreams

1、 Open software , Click on Quick Start Under the Create Project

2、 Pop up and click NEXT

3、 Fill in the project path and project name and click NEXT（ Note that the path should not contain Chinese ）

4、 choice RTL project, Check do not specify sources at this time Indicates that the source file is not specified , Click on next

5、 choice FPGA Click next

You can filter through the options above , You can also enter the model directly to search

6、 single click Finish

7、 Click on + Add new file

8、 choice add or create design sources Back click NEXT

9、 single click Create File, Input file name XXX Then click OK

10、 single click Finish —> single click OK —> single click Yes

11、 double-click TIMER, Input code save

If the font in the editor is too small, you can change the font size by setting ：

13、 Click... On the left Run Synthesis To synthesize , single click OK Then choose Open Synthesized Design, single click OK

14、 First click Sources Jump back to the source file interface , And then click +, Add simulation file

15、 choice Add or create simulation sources Back click Next

16、 single click Create File Then enter the file name , single click OK, single click Finish

single click OK, single click Yes

17、 Double click the corresponding file name to open the file

18、 Enter the code and save （Ctrl+s）

19、 single click Run Simulation Then choose Run behavioral Simulation, Run the simulation

20、 Enter 1ms Then magnify and observe the waveform

You can see that the rising edge of each clock will accumulate one , The simulation is correct

21、 Close the simulation interface , single click SYNTHESIS Then select I/O Planning

22、 Restrict the pins according to the circuit design , Remember to save when you're done

23、 single click OK, Enter the file name and click OK

24、 Click... In the left column Setup Debug

25、 Click continuously in the pop-up window NEXT

26、 Save the configuration of the signal just monitored , single click OK

27、 single click Generate Bitstream, Create a bitstream , To synthesize 、 Layout and wiring 、 Generate bit file

28、 single click Yes, single click OK

29、 Pop up options View Reports, single click OK

30、 single click Open Hardware Manager

For debugging and simulation ,FPGA Support JTAG Debug mode .JTAG(Joint Test Action Group, Joint test working group ) It's an international standard test protocol (IEEE 1149.1 compatible ), It is mainly used for chip internal test . Most advanced devices now support JTAG agreement , Such as DSP、FPGA Devices, etc . The standard JTAG Interface is 4 Line :TMS、 TCK、TDI、TDO, They are mode selection 、 The clock 、 Data input and data output lines .

• TCK– Test clock input
• TDI– Test data input , Data is passed through TDI Input JTAG mouth
• TDO– Test data output , Data is passed through TDO from JTAG output
• TMS– Test mode selection ,TMS Used to set JTAG The mouth is in a certain test Pattern
• Optional pin TRST– Test reset , Input pin , Low level active

31、 The simulator is connected first FPGA plate JTAG Interface , Then connect the computer USB Interface ,FPGA Access to electricity

32、 single click Open target, Pop up Click Auto Connect

33、 single click Program device

34、 single click Run trigger for this ILA core Button trigger

35、 Enlarge the waveform to view

36、 Close debug window

37、 single click OK,FPGA Power on , Finish debugging