Cadence innovus physical implementation series (I) Lab 1 preliminary innovus

I am a snowy fish , a FPGA lovers , The research direction is FPGA Architecture exploration .
Notes sync in my Personal website updated , Welcome to check .
IC/FPGA Design learning exchange group number ： 866169462

The experimental manual and data are from Innovus Lab and Lab Guide Download address

Required for the experiment

1. have access to Cadence Innovus Software
2. The experimental data in the above link has been downloaded

One 、 Import design

The goal is ： open Innovus GUI Interface and import design
In this experiment , Will learn
（1） How to import gate level net tables and libraries to Innovus in , And create floorplan;
（2） Can be familiar with floorplanning The process and power planning technological process ;
（3） You will learn how to use the blind key to check the library , Design .

1. stay InnovusBlk_18_1/FPR/work Open the terminal in the directory , Input innovus Open software ：
   
2. Click on In the menu bar File -> Import Design
   
   The window for importing design will pop up automatically ：
   

Directly click on... Of the five buttons at the bottom of the window Load...:

Choose dtmf.globals file , Click on open：

You can see that the columns of the design import window have been configured .

• dtmf.view The file contains pointers to the timing library and the constraint file .
• dtmf.io File is I/O Assign files , Contains information about core Place around the area I/O Pad instructions .

The introduction of each part of the window is as follows ：

name	effect
Netlist-Verilog	Add the integrated door level Verilog Net watch , namely .v file
LEF Files	Contains physical information about catalogs and components , It also includes wiring layers and DRC The rules
IO Assignment File	Contains for placing IO Pad To core Peripheral instructions , If you did not add this file , The software will randomly place IO pad
MMMC View Definition File	Contains points to the timing library and SDC Pointer to constraint file

Here we have a look dtmf.globals file ：

You can see in this file , Some configurations of the design are defined by many commands , such as gnd/Power The signal , Door level net list to import , Top level unit name , Process library files lef Etc . When importing a design, you only need Load Check this configuration file , You can easily import your own design , So you can write your own design configuration file following this file in the future .

3. Load After the configuration file is completed , Just click OK：
   

Two 、 View design

1. Click on Innovus On the right side Floorplan view Icon ：

Press again F , Place the design in the middle of the window

2. On the right side of the All Colors Panel , Choose Cell , take Pin Shapes Check on , Make it visible .


3. You can use the menu bar Tools -> Log Viewer see log

You can see ,log Contained in the Innovus Information about each step of operation .
4. Select the module on the left side of the design DTMF_INST, Click on Ungroup Icon once , Ungroup ：


Split the module into multiple modules . Double click on these sub modules to see their names and properties ：

In the diagram above , The pink module on the left is the module defined in the imported net list file , On the right is a hard macro or IP.
5. Select a pink module , Click combination , Restructuring .

3、 ... and 、 View the design hierarchy

1. In all objects Without being selected , Click on the Tools->Design Browser：
   
   
   You can see DTMF_CHIP Design level of .

This time, Lab To this end ！ I mainly learned how to import design , Then on Innovus Some basic operations of .