MCDF top level verification scheme

1. summary

Multichannel data shaper （MCDF,multi-channel data formatter）, You can move up （uplink） Multiple channel data passes through the internal FIFO, Finally, the data package （data packet） Send out in the form of .

2. reg_env

• For the verification environment of register module reg_env, Include
  • reg_master_agent, Provide register interface drive signal
  • reg_slave_agent, Provide register interface feedback signal
  • scoreblard, Respectively from the reg_master_agent Internal monitor and reg_slave_agent Internal monitor Obtain monitoring data , And compare the data
    

3. chnl_env

• Verification environment of data channel slave chnl_env The components of include ：
  • chnl_master_agent, Provide uplink incentive data
  • chnl_slave_agent, Provide to simulate arbiter Arbitration signal , And receive outgoing data
  • reg_cfg_agent, Provide configuration signals for analog registers , And receive built-in FIFO Margin signal
  • scoreboard, Respectively from the chnl_master_agent、chnl_slave_agent and reg_cfg_agent Of monitor Receive monitoring data , And right channel The inflow and outflow data of
    

4. arb_env

• Verification environment of arbiter arb_env The components of include ：
  • simulation channel Output interface arbiter_master_agent Three examples of , Used to correct arbiter Provide parallel data input , At the same time arbiter The feedback arbitration signal makes corresponding
  • arbiter_slave_aent, For reception arbiter Output data of , simulation formatter act , Yes arbiter The output signal makes corresponding
  • reg_cfg_agent, Provide configuration signals for analog registers , To three channel Data sources make different priority configurations
  • scoreboard, From three arbiter_master_agent、arbiter_slave_agent and reg_cfg_agent Medium monitor Obtain monitoring data , Yes arbiter The arbitration mechanism to make a pre judgment , And the input and output data are compared according to the priority of prediction
    

5. fmt_env

• Verification environment of shaper fmt_env The components of include ：
  • fmt_master_agent, To simulate arbiter Output data of
  • fmt_slave_agent, To simulate MCDF Downlink data receiving end
  • ref_cfg_agent, Used to simulate the configuration signal of the register , Used to specify the length of the output packet
  • scoreboard, from fmt_master_agent、fmt_slave_agemt and reg_cfg_agemt Of monitor Obtain monitoring data , Predict the output packets by packet length , And formatter Compare the output packets
    

6. Environment integration scheme 1

• Reuse the components of the module validation environment ,reg_master_agent、chnl_master_agent、fmt_slave_agent
• scoreboard It provides a complete data path coverage scheme , That is, from each agent Of monitor The data monitoring port collects data , At the same time establish MCDF Reference model of , Predicted output packets , Finally, compare the data
• virtual sequencer Control how incentives are sent , Coordination

class mcdf_env1 extends uvm_env;
	`uvm_component_utils(mcdf_env1)
	reg_master_agent reg_mst;
	chnl_master_agent chnl_mst1;
	chnl_master_agent chnl_mst2;
	chnl_master_agent chnl_mst3;
	fmt_slave_agent fmt_slv;
	mcdf_virtual_sequencer virt_sqr;
	mcdf_scoreboard sb;
	...
	function void build_phase(uvm_phase phase);
		super.build_phase(phase);
		reg_mst = reg_master_agent::type_id::create("reg_mst", this);		//  establish 5 individual agent
		chnl_mst1 = chnl_master_agent::type_id::create("chnl_mst1", this);
		chnl_mst2 = chnl_master_agent::type_id::create("chnl_mst2", this);
		chnl_mst3 = chnl_master_agent::type_id::create("chnl_mst3", this);
		fmt_slv = fmt_slave_agent::type_id::create("fmt_slv", this);
		virt_sqr = mcdf_virtual_sequencer::type_id::create("virt_sqr", this);
		sb = mcdf_scoreboard::type_id::create("sb", this);
	endfunction
	
	function void connect_phase(uvm_phase phase);
		super.connect_phase(phase);
		//virtual sequencer connect
		virt_sqr.reg_sqr = reg_mst.sequencer;			// vsqr And 5 individual agent Medium sqr Handle connection 
		virt_sqr.chnl_sqr1 = chnl_mst1.sequencer;
		virt_sqr.chnl_sqr2 = chnl_mst2.sequencer;
		virt_sqr.chnl_sqr3 = chnl_mst3.sequencer;
		virt_sqr.fmt_sqr = fmt_slv.sequencer;
		//monitor transactions to scoreboard
		reg_mst.monitor.ap.connect(sb.reg_export);		// TLM Communication establish connection 
		chnl_mst1.monitor.ap.connect(sb.chnl1_export);
		chnl_mst2.monitor.ap.connect(sb.chnl2_export);
		chnl_mst3.monitor.ap.connect(sb.chnl3_export);
		fmt_slv.monitor.ap.connect(sb.fmt_export);
	endfunction
endclass

7. Environment integration scheme II

• Option two Reuse the module environment xxx.env, Intuitively, there are many components
• You only need to integrate agent To configure （build Stage ） For different modes （passive or active）, Reduce the additional cost of the top-level environment
• There is no need to implement new scoreboard
• Both schemes need new implementation virtual sequencer and virtual sequence, Used to generate the top-level test sequence

class mcdf_env1 extends uvm_env;
	`uvm_component_utils(mcdf_env1)
	reg_env reg_e;		//  Reuse environment 
	chnl_env chnl_e1;
	chnl_env chnl_e2;
	chnl_env chnl_e3;
	fmt_env fmt_e;
	arb_env arb_e;
	mcdf_virtual_sequencer virt_sqr;
	function void build_phase(uvm_phase phase);
		super.build_phase(phase);
		// Configure the sub environment as active or passive Pattern 
		uvm_config_db#(int)::set(this, "reg_e.slave", "is_active", UVM_PASSIVE);	//  Configure before creating 
		uvm_config_db#(int)::set(this, "chnl_e1.slave", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "chnl_e1.reg_cfg", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "chnl_e2.slave", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "chnl_e2.reg_cfg", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "chnl_e3.slave", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "chnl_e3.reg_cfg", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "arb_e.master1", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "arb_e.master2", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "arb_e.master3", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "arb_e.slave", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "arb_e.reg_cfg", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "fmt_e.master", "is_active", UVM_PASSIVE);
		uvm_config_db#(int)::set(this, "fmt_e.reg_cfg", "is_active", UVM_PASSIVE);
		// Create a sub environment 
		reg_e = reg_env::type_id::create("reg_e", this);
		chnl_e1 = chnl_env::type_id::create("chnl_e1", this);
		chnl_e2 = chnl_env::type_id::create("chnl_e2", this);
		chnl_e3 = chnl_env::type_id::create("chnl_e3", this);
		virt_sqr = mcdf_virtual_sequencer::type_id::create("virt_sqr", this);
	endfunction
	function void connect_phase(uvm_phase phase);
		super.connect_phase(phase);
		//virtual sequencer connection
		virt_sqr.reg_sqr = reg_e.master.sequencer;		// vsqr And 5 individual agent Medium sqr Handle connection 
		virt_sqr.chnl_sqr1 = chnl_e1.master.sequencer;
		virt_sqr.chnl_sqr2 = chnl_e2.master.sequencer;
		virt_sqr.chnl_sqr3 = chnl_e3.master.sequencer;
		virt_sqr.fmt_sqr = fmt_e.slave.sequencer;
	endfunction
endclass

8. conclusion UVM The advantages of the reuse environment

• The verification environment of each module is encapsulated independently , There is no need to reserve data ports , Therefore, it is convenient for further integration and reuse of the environment
• because UVM Self phase Mechanism , When coordinating the sub environments at the top , There is no need to consider the problem that the object handle reference is suspended due to the instantiation order between sub environments
• Because the test sequence of the sub environment is relatively independent , This enables the top layer to reuse the sub environment test sequence virtual sequence when , No additional migration costs are required
• UVM Provide config_db Configuration mode , The structure and operation mode of the overall environment can be changed from tree config Get in object , This also allows the top-level environment to be different uvm_test Conduct centralized management configuration