Verilog daily question (vl6 data series to parallel circuit)

Title Description

         Realize serial parallel conversion circuit , Input end input sheet bit data , Whenever this module receives 6 After inputting data , The output end outputs the spliced 6bit data . The input end and upstream of this module adopt valid-ready Two way handshake system , The downstream and downstream outputs are used valid-only handshake mechanisms . When splicing data, the data received first is put into data_b Low position .

         The interface of the circuit is shown in the figure below .valid_a Used to indicate data entry data_a The effectiveness of the ,valid_b Used to indicate data output data_b The effectiveness of the ;ready_a Used to indicate whether the module is ready to receive upstream data , Always pull up in this module ;clk It's a clock signal ;rst_n It is an asynchronous reset signal .

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         The principle of handshake agreement is ： When Valid and Ready When the signal is highly effective at the same time , Data is transmitted on the rising edge of the clock .

The detailed code is as follows ：

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    // It can be seen from the oscillogram that ,ready_a Always set the high level , That is, it is always ready to receive 
    always @(posedge clk or negedge rst_n ) begin
       if(!rst_n)
              ready_a <= 0;
       else
              ready_a <= 1;
    end
    
    // Count the effective signals , And use a data_in To save the data 
    // also valid_a=0 Time does not clear , Will work with the follow-up valid_a=1 Data splicing when 
    reg [3:0] num;
    reg [5:0] data_in;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            num <=0;
            data_in <=0;
        end
        else if(valid_a) begin
            num <= (num==5)? 0:num+1;
            data_in = {data_a,data_in[5:1]}; // Store data and shift to save 
        end
    end
    
    // Output 
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            data_b <=0; 
            valid_b <=0;
        end
        else if(num==5) begin
            valid_b <= 1 ;
            data_b <= data_in;
        end
        else 
            valid_b <=0;// High level signal with only one cycle 
    end
    
endmodule

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Done!