Verilog daily question (vl27 settable counter)

Title Description

Please write a hexadecimal counter module , The counter output signal is incremented every time it reaches 0, Give an indication signal zero, When the set signal set Is valid , Set the current output as the input value set_num.
The interface signal diagram of the module is as follows ：

 

  Ideas ： I can't see clearly in this oscillogram , actually rst_n Set up 1 after num For the first 0, Change again 1, I didn't pay attention to this at first, and I don't know why I was wrong . So the output number There must be a delay of one cycle .

Here we add an intermediate counter num To postpone the clock , When num<=num+1 when ,number <=num, because always Blocks are parallel , So at this time number assignment num, Nonblocking assignment num<=num+1 A simultaneous , And at this time num=0;

Thought of expansion , If you add another num2<=number, The assignment will be delayed by another cycle . You can add intermediate variables to increase the delay .

（ This method can be recorded ）

  The rest of the idea is simple ,num=0 when zero=1,num from 0-15 loop .

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
	reg [3:0]num;
	
	always @(posedge clk or negedge rst_n)begin
		if (!rst_n) zero <= 1'd0;
		else if (num == 0) zero <= 1;
		else zero <= 1'b0;
    end
		
	always @(posedge clk or negedge rst_n) begin
		if (!rst_n) num <= 4'b0;
		else if(set) num <= set_num;
		else num <= num + 1'd1;
	end

	always @(posedge clk or negedge rst_n) beign
		if (!rst_n) number <= 1'd0; 
		else   number <= num;
	end		 		

endmodule

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