Principle and usage setting of large page memory

The principle of improving performance by the size of memory pages
First , We need to review a small part of the principles of computer composition , This is important for understanding large memory paging JVM Performance improvement is beneficial .

What is memory paging ？
We know ,CPU Memory is accessed through addressing .32 position CPU The addressing width of is 0~0xFFFFFFFF , The calculated size is 4G, In other words, the maximum supported physical memory is 4G.

But in practice , Encountered such a problem , The program needs to use 4G Memory , The available physical memory is less than 4G, Cause the program to have to reduce the memory consumption .
In order to solve such problems , modern CPU Introduced MMU（Memory Management Unit Memory management unit ）.

MMU The core idea of is to use virtual address instead of physical address , namely CPU Use virtual addresses when addressing , from MMU Responsible for mapping virtual addresses to physical addresses .
MMU The introduction of , Solved the limitation of physical memory , For the program , It's like you're using it 4G Memory is the same .

paging (Paging) It's using MMU On the basis of , A memory management mechanism is proposed . It keeps the virtual address and physical address in a fixed size （4K） Split into pages (page) And page frames (page frame), And make sure the page is the same size as the page frame .

Such mechanism , In terms of data structure , Ensures efficient access to memory , And make OS Can support discontinuous memory allocation .
When the program memory is not enough , You can also transfer infrequently used physical memory pages to other storage devices , For example, disk. , This is the familiar virtual memory .

Mentioned above , Virtual address and physical address need to be mapped , Can we make CPU Normal work .
Mapping requires storing mapping tables . In modern times CPU Architecture , The mapping relationship is usually stored in physical memory, which is called a page table (page table) The place of .
Here's the picture ：

From this picture , Can be seen clearly CPU And page table , The interaction between physical memory .

Further optimization , introduce TLB（Translation lookaside buffer, Page table register buffer ）
It can be seen from the previous section that , Page tables are stored in memory . We know CPU Access memory via bus , It must be slower than directly accessing registers .
To further optimize performance , modern CPU Architecture introduces TLB, It is used to cache some frequently accessed page table contents .
Here's the picture ：

contrast 9.6 That picture , Add... In the middle TLB.

Why support large memory paging ？
TLB It is limited. , There is no doubt about that . When exceeding TLB When the storage limit of , It will happen TLB miss, after ,OS Will command CPU To access the page table in memory . If it happens frequently TLB miss, The performance of the program will decline quickly .

In order to make TLB You can store more page address mapping relationships , Our approach is to increase the size of memory pages .

If a page 4M, Compare a page 4K, The former can make TLB More storage 1000 Page address mapping relationship , The performance improvement is considerable .

Set large page memory in virtual machine ：

echo 1024 > /proc/sys/vm/nr_hugepages 2G Memory settings for 256,4G Memory settings 512.