Synchronous FIFO based on shift register

As shown in the figure , Officially provided by Xilinx FIFO IP in , Sync FIFO（Common Clock） Can be BRAM、DRAM And shift register constitute , Or built-in FIFO constitute , asynchronous FIFO（Independent Clocks） Can be BRAM、DRAM And built-in FIFO constitute .
This paper mainly realizes Synchronization based on shift register FIFO.
The realization idea is ：
Set a counter , Record the present FIFO Number of internal data , External each direction FIFO Write a data , The shift register shifts once , The position of reading data is based on FIFO The number of internal data .
Here is the code for implementation ：

Code

`timescale 1ns / 1ps
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// Create Date: 2022/07/22 16:43:50