A brief introduction to Verilog mode

verilog-mode What is it?
Introduction to the official website （https://www.veripool.org/wiki/verilog-mode）:
Verilog-mode.el is the extremely popular free Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time. It supports AUTOs and indentation in Emacs for traditional Verilog (1394-2005), the Open Verification Methodology (OVM) and SystemVerilog (1800-2005/1800-2009).
Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand SystemVerilog “.*” port instantiations, to see what ports will be connected by the simulators.
Simply put, support Verilog、SystemVerilog（ Include UVM） Of emacs Syntax highlight file . Mentioned Verilog-mode Support Autos—— That's the point today .

Verilog-mode By Michael McNamara [email protected] and Wilson Snyder [email protected] To write . Here's the thing , This verilog-mode Keep it updated every month .

It is worth mentioning that Wilson Snyder Namely SystemVerilog Open source emulator Verilator The author of .
verilog-mode Autos What are the features
Hand written verilog Code ：

module example (/*AUTOARG*/);
  input i;
  output o;
  /*AUTOINPUT*/
  /*AUTOOUTPUT*/
  /*AUTOREG*/

  inst inst (/*AUTOINST*/);

  always @ (/*AUTOSENSE*/) begin
    o = i;
  end

endmodule

from Autos After processing the Verilog Code ：

module example (/*AUTOARG*/
  // Outputs
  lower_out, o,
  // Inputs
  lower_inb, lower_ina, i
  );
  input i;
  output o;
  /*AUTOINPUT*/
  // Beginning of automatic inputs
  input  lower_ina; // To inst of inst.v
  input  lower_inb; // To inst of inst.v
  // End of automatics
  /*AUTOOUTPUT*/
  // Beginning of automatic output
  output lower_out; // From inst of inst.v
  // End of automactics
  /*AUTOREG*/
  // Beginning of automatic regs
  reg    o;
  // End of automatics

  inst inst (/*AUTOINST*
             // Outputs
             .lower_out (lower_out),
             // Inputs
             .lower_inb (lower_inb),
             .lower_ina (lower_ina));

  always @ (/*AUTOSENSE*/i) begin
    o = i;
  end

You can see ,verilog-mode Automatically analyze ：
Port input and output of the module
Internal variables
Sensitive signal list
Extract the port definition of the sub module
Automatically extracting the port definitions of sub modules to connect is the focus of today's focus . In general , When we instantiate the module, most of the signal names are consistent with the names defined by the sub module . As in the above code ：

  inst inst (/*AUTOINST*
             // Outputs
             .lower_out (lower_out),
             // Inputs
             .lower_inb (lower_inb),
             .lower_ina (lower_ina));

Handling of special connection relationship
But often when we connect to the top layer, we will change the name . such as module A There is an output port dat_o,module B There is an input port dat_i, How can the two be connected ？ Define template AUTO_TEMPLATE, as follows ：
Hand written verilog：

/* A AUTO_TMEPLATE (
  .dat_o (dat_a2b),
)
*/
A u_A (/*AUTOINST*/);

/* B AUTO_TEMPLATE (
  .dat_i (dat_a2b),
)
*/
B u_B (/*AUTOINST*/);

from Autos After processing the verilog Code ：

/* A AUTO_TMEPLATE (
  .dat_o (dat_a2b),
)
*/
A u_A (/*AUTOINST*/
       // Outputs
       .dat_o  (dat_a2b));  // Templated

/* B AUTO_TEMPLATE (
  .dat_i (dat_a2b),
)
*/
B u_B (/*AUTOINST*/
       // Inputs
       .dat_i  (dat_a2b));  // Templated

Where to find sub module definitions ？
The default rules ：
Find... Under the current folder
What if I can't find it at present , Specify the search path （ And verilog Parameters of the simulator -y equally ）
Usage method ： On the top floor endmodule Specify later verilog-library-directories, as follows ：

endmodule // top

// Local Variables:
// verilog-library-directories:("." "subdir" "subdirs")
// End:

In addition to writing templates, what else need to be done ？
It only needs Ctrl-C Ctrl-A, That's it .
If you modify a sub module or template , Press again Ctrl-C Ctrl-A.
More functions

    verilog-auto-arg          for AUTOARG module instantiations
    verilog-auto-ascii-enum   for AUTOASCIIENUM enumeration decoding
    verilog-auto-assign-modport for AUTOASSIGNMODPORT assignment to/from modport
    verilog-auto-inout        for AUTOINOUT making hierarchy inouts
    verilog-auto-inout-comp   for AUTOINOUTCOMP copy complemented i/o
    verilog-auto-inout-in     for AUTOINOUTIN inputs for all i/o
    verilog-auto-inout-modport  for AUTOINOUTMODPORT i/o from an interface modport
    verilog-auto-inout-module for AUTOINOUTMODULE copying i/o from elsewhere
    verilog-auto-inout-param  for AUTOINOUTPARAM copying params from elsewhere
    verilog-auto-input        for AUTOINPUT making hierarchy inputs
    verilog-auto-insert-lisp  for AUTOINSERTLISP insert code from lisp function
    verilog-auto-insert-last  for AUTOINSERTLAST insert code from lisp function
    verilog-auto-inst         for AUTOINST instantiation pins
    verilog-auto-star         for AUTOINST .* SystemVerilog pins
    verilog-auto-inst-param   for AUTOINSTPARAM instantiation params
    verilog-auto-logic        for AUTOLOGIC declaring logic signals
    verilog-auto-output       for AUTOOUTPUT making hierarchy outputs
    verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
    verilog-auto-reg          for AUTOREG registers
    verilog-auto-reg-input    for AUTOREGINPUT instantiation registers
    verilog-auto-reset        for AUTORESET flop resets
    verilog-auto-sense        for AUTOSENSE or AS always sensitivity lists
    verilog-auto-tieoff       for AUTOTIEOFF output tieoffs
    verilog-auto-undef        for AUTOUNDEF \=`undef of local \=`defines
    verilog-auto-unused       for AUTOUNUSED unused inputs/inouts
    verilog-auto-wire         for AUTOWIRE instantiation wires

    verilog-read-defines      for reading \=`define values
    verilog-read-includes     for reading \=`includes

See the help document on the official website for details ：
https://www.veripool.org/projects/verilog-mode/wiki/Verilog-mode-Help

verilog-mode download 、 install
New version of the GNU Emacs Bring their own verilog-mode, If you need the latest verilog-mode It can be downloaded from the official website ：
https://www.veripool.org/projects/verilog-mode/wiki/Installing

VIM What about users ？
It can be used VIM transfer shell Command execution （emacs Batch mode ）, for example ：
:!emacs --batch <filenames.v> -f verilog-batch-auto