1. Mx6u-alpha development board (GPIO interrupt experiment)

One 、 review STM32 Interrupt the system

​ 1、STM32 Interrupt vector table
​ ARM Chip from 0X00000000 Began to run , Execution instruction . The interrupt vector table is stored at the beginning of the program . The main function of the interrupt vector table is to describe the interrupt service function corresponding to the interrupt .
​ about STM32 The address at the beginning of the code stores the top pointer of the stack .

2、 Interrupt vector offset
commonly ARM from 0X000000000 Address starts running , about STM32 We set the connection first address to 0X8000000.
If the code must start from 0X8000000 Began to run , Then I need to tell you soc kernel . That is, set the interrupt vector offset . Set up SCB Of VTOR The register is the starting address of the new interrupt vector table .
3、NVIC Interrupt controller .
NVIC Is to interrupt the management organization . Enable and disable the specified interrupt 、 Set interrupt priority .
4、 Preparation of interrupt service function
Interrupt service function is what interrupt does .

Two 、Cortex-A7 Interrupt the system

​ 1、Cortex-A Interrupt vector table
​ Cortex-A Interrupt vector table has 8 A break , It focuses on IRQ.Cortex-A The interrupt vector table of needs to be defined by the user .
​ 2、 Interrupt vector offset
​ Our bare metal experience is from 0X87800000 At the beginning , So set the interrupt vector offset .
​ 3、GIC Interrupt controller .
​ Same as NVIC equally ,GIC Used to manage Cortex-A The interrupt .GIC Switch interrupts are provided , Set interrupt priority .
​ 4、IMX6U Interrupt number
​ To distinguish between different interrupts , Interrupt number is introduced .ID0_{ID15 It's for SGI,ID16}ID31 It's for PPI. The rest ID32~1019 to SPI, That is, the key is interrupted 、 Serial interrupt ....
​ 6ULL Support 128 A break .
​ 4、 Preparation of interrupt service function
​ One is IRQ Preparation of interrupt service function , The other is in IRQ Find and run the specific peripheral interrupt service function in the interrupt service function ,

3、 ... and 、GIC Interrupt controller

Four 、 Interrupt experiment preparation

​ 1、 Write key interrupt routine .
​ KEY0 Use UART1_CTS This IO. To write UART1_CTS Interrupt code of .
​ 2、 modify start.S
​ Add interrupt vector table , Write reset interrupt service function and IRQ Interrupt service function .
​ Write reset interrupt service function , The contents are as follows ：
​ ①、 close I,D Cache and MMU.
​ ②、 Set up the processor 9 Under the working mode of SP The pointer . To use interrupts, you must set IRQ Mode of SP The pointer . Simply set all modes directly SP The pointer .
​ ③、 eliminate bss paragraph .
​ ④、 Jump to the C function , That is to say main function

3、CP15 Coprocessor

MRC: take CP15 The register data in the coprocessor reads ARM In the register .
MRC It's reading CP15 register , MCR Is to write CP15 register , MCR The command format is as follows ：

MCR{cond} p15, , , , ,

MRC p15, 0, r0, c0,c0,0
Now close I,D ache and MMU, open Cortex-A7 Refer to the manual to 105 page , find SCTLR register . That is, the system control register , This register bit0 For opening and closing MMU,bit1 Control alignment ,bit2 control D Cache On and off .Bit11 Used to control branch prediction .Bit12 Used to control the I Cache.
Interrupt vector offset setting
Write the new interrupt vector table header address to CP15 Coprocessor VBAR register .
MCR{cond} p15, , , , ,
MRC p15,0,r0,c12,c0,0 //
MCR p15,0,r0,c12,c0,0

IRQ Interrupt service function
mrc p15, 4, r1, c15, c0, 0 Read CP15 Of CBAR register .CBAR The register holds GIC The first address of the register group of the controller .GIC Register group offset 0x1000_{0x1fff by GIC The dispenser of .0x2000}0x3fff by CPU Interface . Means we can visit GIC The controller is ！
In the code ,R1 Register bar saves GIC Controller CPU Interface end base address . Read CPU Interface segment GICC_IAR The value of the register is saved to R0 In the register . It can be downloaded from GICC_IAR Of bit9~0 Read interrupt ID, We read interrupt ID The purpose of is to get the corresponding interrupt processing function .
system_irqhandler It is the specific interrupt handling function , This function has one parameter , by GICC_IAR Register value .
system_irqhandler After handling the specific interrupt , The corresponding interrupt ID Value written to GICC_EOIR In the register .

.global _start  				/*  Global label  */

/*
 *  describe ：	_start function , The first is the creation of interrupt vector table 
 *  Reference documents :ARM Cortex-A(armV7) Programming manual V4.0.pdf P42,3 ARM Processor Modes and Registers（ARM Processor models and registers ）
 * 		 	ARM Cortex-A(armV7) Programming manual V4.0.pdf P165 11.1.1 Exception priorities( abnormal )
 */
_start:
	ldr pc, =Reset_Handler		/*  Reset interrupt  					*/	
	ldr pc, =Undefined_Handler	/*  Undefined interrupt  					*/
	ldr pc, =SVC_Handler		/* SVC(Supervisor) interrupt  		*/
	ldr pc, =PrefAbort_Handler	/*  Prefetch termination interrupt  					*/
	ldr pc, =DataAbort_Handler	/*  Data termination interrupt  					*/
	ldr	pc, =NotUsed_Handler	/*  Unused interrupt 					*/
	ldr pc, =IRQ_Handler		/* IRQ interrupt  					*/
	ldr pc, =FIQ_Handler		/* FIQ( Fast interrupt ) Undefined interrupt  			*/

/*  Reset interrupt  */	
Reset_Handler:

	cpsid i						/*  Turn off global interrupt  */

	/*  close I,DCache and MMU 
	 *  Take a read - Change - The way of writing .
	 */
	mrc     p15, 0, r0, c1, c0, 0     /*  Read CP15 Of C1 Register to R0 in        		        	*/
    bic     r0,  r0, #(0x1 << 12)     /*  eliminate C1 The register of bit12 position (I position ), close I Cache            	*/
    bic     r0,  r0, #(0x1 <<  2)     /*  eliminate C1 The register of bit2(C position ), close D Cache    				*/
    bic     r0,  r0, #0x2             /*  eliminate C1 The register of bit1(A position ), Turn off alignment 						*/
    bic     r0,  r0, #(0x1 << 11)     /*  eliminate C1 The register of bit11(Z position ), Turn off branch prediction 					*/
    bic     r0,  r0, #0x1             /*  eliminate C1 The register of bit0(M position ), close MMU				       	*/
    mcr     p15, 0, r0, c1, c0, 0     /*  take r0 The value in the register is written to CP15 Of C1 In the register 	 				*/

	
#if 0
	/*  Assembly version setting interrupt vector table offset  */
	ldr r0, =0X87800000

	dsb
	isb
	mcr p15, 0, r0, c12, c0, 0
	dsb
	isb
#endif
    
	/*  Set the stack pointer in each mode ,
	 *  Be careful ：IMX6UL The stack is growing downward ！
	 *  The stack pointer address must be 4 Byte address aligned ！！！
	 * DDR Range :0X80000000~0X9FFFFFFF
	 */
	/*  Get into IRQ Pattern  */
	mrs r0, cpsr
	bic r0, r0, #0x1f 	/*  take r0 Low in register 5 A reset , That is to say cpsr Of M0~M4 	*/
	orr r0, r0, #0x12 	/* r0 Or on the 0x13, Said the use of IRQ Pattern 					*/
	msr cpsr, r0		/*  take r0  Data written to cpsr_c in  					*/
	ldr sp, =0x80600000	/*  Set up IRQ The stack header address in mode is 0X80600000, The size is 2MB */

	/*  Get into SYS Pattern  */
	mrs r0, cpsr
	bic r0, r0, #0x1f 	/*  take r0 Low in register 5 A reset , That is to say cpsr Of M0~M4 	*/
	orr r0, r0, #0x1f 	/* r0 Or on the 0x13, Said the use of SYS Pattern 					*/
	msr cpsr, r0		/*  take r0  Data written to cpsr_c in  					*/
	ldr sp, =0x80400000	/*  Set up SYS The stack header address in mode is 0X80400000, The size is 2MB */

	/*  Get into SVC Pattern  */
	mrs r0, cpsr
	bic r0, r0, #0x1f 	/*  take r0 Low in register 5 A reset , That is to say cpsr Of M0~M4 	*/
	orr r0, r0, #0x13 	/* r0 Or on the 0x13, Said the use of SVC Pattern 					*/
	msr cpsr, r0		/*  take r0  Data written to cpsr_c in  					*/
	ldr sp, =0X80200000	/*  Set up SVC The stack header address in mode is 0X80200000, The size is 2MB */

	cpsie i				/*  Turn on global interrupt  */
#if 0
	/*  Can make IRQ interrupt  */
	mrs r0, cpsr		/*  Read cpsr Register value to r0 in  			*/
	bic r0, r0, #0x80	/*  take r0 In the register bit7 Zero clearing , That is to say CPSR Medium I A reset , It means to allow IRQ interrupt  */
	msr cpsr, r0		/*  take r0 Re write to cpsr in  			*/
#endif

	b main				/*  Jump to main function  			 	*/

/*  Undefined interrupt  */
Undefined_Handler:
	ldr r0, =Undefined_Handler
	bx r0

/* SVC interrupt  */
SVC_Handler:
	ldr r0, =SVC_Handler
	bx r0

/*  Prefetch termination interrupt  */
PrefAbort_Handler:
	ldr r0, =PrefAbort_Handler	
	bx r0

/*  Data termination interrupt  */
DataAbort_Handler:
	ldr r0, =DataAbort_Handler
	bx r0

/*  Unused interrupts  */
NotUsed_Handler:

	ldr r0, =NotUsed_Handler
	bx r0

/* IRQ interrupt ！ a key ！！！！！ */
IRQ_Handler:
	push {lr}					/*  preservation lr Address  */
	push {r0-r3, r12}			/*  preservation r0-r3,r12 register  */

	mrs r0, spsr				/*  Read spsr register  */
	push {r0}					/*  preservation spsr register  */

	mrc p15, 4, r1, c15, c0, 0 /*  from CP15 Of C0 The value in the register to R1 In the register 
								*  Reference documents ARM Cortex-A(armV7) Programming manual V4.0.pdf P49
								* Cortex-A7 Technical ReferenceManua.pdf P68 P138
								*/							
	add r1, r1, #0X2000			/* GIC Base address plus 0X2000, That is to say GIC Of CPU Interface end base address  */
	ldr r0, [r1, #0XC]			/* GIC Of CPU Interface end base address plus 0X0C Namely GICC_IAR register ,
								 * GICC_IAR The register holds the interrupt number of the current interrupt , We have to rely on 
								 *  This interrupt number is used to absolutely call which interrupt service function 
								 */
	push {r0, r1}				/*  preservation r0,r1 */
	
	cps #0x13					/*  Get into SVC Pattern , Allow other interrupts to go in again  */
	
	push {lr}					/*  preservation SVC Mode lr register  */
	ldr r2, =system_irqhandler	/*  load C Language interrupt handler to r2 In the register */
	blx r2						/*  function C Language interrupt handler , With a parameter , Save in R0 In the register  */

	pop {lr}					/*  After execution C Language interrupt service function ,lr Out of the stack  */
	cps #0x12					/*  Get into IRQ Pattern  */
	pop {r0, r1}				
	str r0, [r1, #0X10]			/*  Interrupt execution complete , Write EOIR */

	pop {r0}						
	msr spsr_cxsf, r0			/*  recovery spsr */

	pop {r0-r3, r12}			/* r0-r3,r12 Out of the stack  */
	pop {lr}					/* lr Out of the stack  */
	subs pc, lr, #4				/*  take lr-4 Assign to pc */
	
	

/* FIQ interrupt  */
FIQ_Handler:

	ldr r0, =FIQ_Handler	
	bx r0