[FPGA chaos] implementation of FPGA based chaotic system Verilog

1. Software version

Quartusii12.1

2. This algorithm fpga Implementation process

here , The main formula we use is ：

First , We use MATLAB Conduct simulation , The results are as follows ：

then , We use FPGA To implement

 

  here , In style A=10,B=28,C=8/3 Is a typical parameter .

For ease of use FPGA Realize continuous chaotic system , May adopt Euler The algorithm discretizes the formula , The following discretization equation is obtained ：

        When △T Small enough , Take... For example △T =0.001S, The above two systems have the same dynamic characteristics , here （2） The corresponding discrete equation of the equation is ：

  In this system, we use IEEE754 Single precision representation , You can get the following results .

0.99：3F7D70A3

0.999：3F7FBE76

0.01：3C23D70A

0.001：3A83126E

0.028：3CE56041

0.9973333：3F7F513C

2.1 floating-point Multiplier

    This multiplier , We use IP Nuclear to complete .

chart 1 Multiplier IP Nuclear generation step 1

chart 2 Multiplier IP Nuclear generation step 2

 

chart 3 Multiplier IP Nuclear generation step 3

Keep the default settings for the following .

complete , Simulate the core , The simulation results are as follows ：

chart 4 Multiplier IP Nuclear simulation

2.2 floating-point Add / Subtracter

chart 5 adder IP Nuclear generation

The rest remain default , Complete the adder IP The setting of the core .

The simulation results are as follows ：

chart 6 adder IP Nuclear simulation

2.3 Delay module design

    Because there is n+1, and n therefore , There is a delay relationship between . Delay can be achieved only through triggers . The simulation results are as follows ：

chart 7 Delay module simulation results

3 System overall module design

    We just need to delay the output of each stage , You can get the right side of the formula x(n),y(n),z(n).

build , The schematic diagram is as follows ：

chart 8 The schematic diagram of

 

 

 

  All the top-level schematic diagrams are as follows ：

chart 11 System top level schematic diagram

We synthesize the system , The results are as follows ：

 

chart 12 System comprehensive resource occupation diagram

From above , We can see that the whole system takes up less resources , Mainly applied to a large number of multipliers .

Functional simulation of the system ： The results are as follows ：

chart 13 Overall simulation results of the system

3. reference

[1] Xie Guobo , Chen Pinghua , Cai Zhaobo . A quadratic trinomial universal expression FPGA Chaos generator design [J]. Microcomputer information , 2009.A07-03