Mastering JESD204B (3) – Debugging of AD6676

Based on AD6676-204B debugging chapter 3

1. Purpose:
   The purpose of this section is mainly about DMA transfers.In the previous section, we mentioned that the overall data flow of the project is the data collected by AD. First, the data is transmitted to ZYNQ FPGA through the Aurora interface. The PL end of ZYNQ receives the data sent by Aurora, and then transmits the data through the DMA interface.to the PS side, and then the PS transmits the data to the host computer through the network.The host computer stores the received data as a file for subsequent processing.
   2. Block diagram:
   The specific block diagram is as follows:
   3. Implementation principle:
   The most basic interfaces we want to use here are the Aurora and DMA interfaces. Let's take a look at the IP configuration of Aurora:
   First, we need to determine the line rate of Aurora transmission;
   Second, what is the reference clock corresponding to the line rate;
   Third, then its initialization clock and dynamic configuration clock, these twoThe default clock is 100MHz;
   Fourth, the flow control configuration of the Aurora interface is here, we do not need flow control, so choose none here;
   
   DMA is implemented on the ZYNQ side.Therefore, we must first build the minimum system of ZYNQ.Later, I will publish an article about building the ZYNQ system. Here we will skip this part and develop it directly in the built project.
   
   
   It can be seen that as long as you send data to the ZYNQ interface according to the A X iStream interface, you can receive data on the software sideInterrupt to DMA and give data.
   
   This will enable data to pass through Aurora to ZYNQA complete process from the PL end of the ZYNQ to the ps end of the ZYNQ.