RT thread migration to s5p4418 (I): scheduler

S5P4418,Cortex-A9 series .
Combined with the RT-Thread Kernel Implementation （ 6、 ... and ）： Time slice and S5P4418 Bare metal development （ fourteen ）：TIMER Code for .

SysTick & PendSV

RT-Thread The implementation of thread scheduling two core interrupts .
SysTick Update system timebase .PendSV Do context switching .

• SysTick stay S5P4418 of use timer0 Instead of . cycle 10ms, Note that the interrupt service function should clear the interrupt flag bit .

void SysTick_Config(){
     //  It's just a change of name 
    IP_RESET_REGISTER1 |= (1 << 4);     //  Close reset 

    TCFG0 |= (250 - 1);     // PCLK = 200MHz 200000000 / 16 / 250 = 50000;
    TCFG1 |= 0x4;
    TCNTB0 = 500;          // 500 = 10ms
    TCON |= (1 << 1);

    // vic_init(23, (u32)timer0_ISR); //  register VIC
    vic_init(23, (u32)SysTick_Handler);  //  register VIC

    TINT_CSTAT |= (1 << 0); //  Interrupt enable 
    TCON &= ~(1 << 1);
    TCON |= ((1 << 3) | (1 << 0));  //  Automatic reload , Start timer 
}

void SysTick_Handler(void)
{
    
    /*  Enter interrupt  */
    rt_interrupt_enter();

    rt_tick_increase();

    TINT_CSTAT |= (1 << 5); //  Clear interrupt flag 

    /*  Leave interrupt  */
    rt_interrupt_leave();
}

• Choose another one that can replace PendSV The interrupt , because S5P4418 All interrupts on can be triggered by software , So choose one that nobody uses , I chose 63 Interrupt number . The key point is to modify the interrupt service program .

PendSV_Handler

• Coterx-M3 Scheduling in RT-Thread Kernel Implementation （ One ）： Threads and scheduling It is more clearly described in . A few steps to switch contexts ：
  • Hardware auto save xPSR, PC, LR, R12 as well as R3‐R0 To the thread stack .
  • Take out the source thread's psp, The top of the stack sp, preservation r4 - r11 To sp Point to . This completes the task of saving the above .
  • Switch below , Take the... Of the thread to be run sp value , No sp register , load r4 - r11, then sp Write the value back to sp register .
  • After exiting the interrupt , The hardware is automatically loaded from the stack xPSR, PC, LR, R12 as well as R3‐R0.

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• and A9 There is no automatic save operation when responding to an interrupt , either MSP and PSP register . You can also press the above... When transplanting 4 Step by step .
  • First step , preservation CPSR, PC, LR, R12 as well as R3‐R0 To the thread stack .CPU Get into IRQ After the model ,sp The register is in this mode r13_irq. The thread I set up runs in privileged mode , Its sp Registers should r13_svc. So first switch back to the mode before the interrupt .
  • then push that 8 A register , Here we need to pay attention to the order , The next step is to explain .
  • The second step , preservation r4 - r11, At this time, the mode is switched , It is already the stack of the source thread , direct push.
  • The third step , Switch below , and M3 The operation is the same .
  • Step four ,A9 The previous mode will be automatically saved when entering the interrupt CPSR To SPSR, When exiting an interrupt , If LDMFD Equal command band ’^’,CPSR Automatically written back by hardware . So recover PC, LR, R12 as well as R3‐R0 when , First of all, I will CPSR write in SPSR in , For the convenience of cpsr Value , When saving in the first step CPSR the last one push. meanwhile struct exception_stack_frame Medium rt_uint32_t psr Put it on the top .

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Other details will be added later .

engineering

103_rtt2a9