(4) UART application design and simulation verification 2 - TX module design (stateless machine)

Preface ： Looking back on this small project again, it has been a few months , In the follow-up study , The new teacher is constantly emphasizing , Try to use less state machines in practical work , When sorting out the article, I forgot what he said at that time . So I try to rewrite it myself UART, Organize a version without a state machine .

Here are a few basic logical points to review again ：
1） The complete one frame data format contains ： Start bit , Valid data bits , Check bit , Stop bit ;
2） Calculation sheet bit Data transmission time ： utilize baoud（ Baud rate ） and clk（ The system clock ）, Baud rate unit bit per second, The clock Hz Company time per second , So the clock divided by the baud rate is time per bit, That is, every bit Corresponding to how many clock cycles ;
3） Reference signal ： Transmission signal baoud_cnt_half, Every time bit Half way through the count , To transfer data ; Switch the counting signal baoud_cnt_end, Every time bit When the count is finished , Enter the next counting cycle ; Bit count bit_cnt, Calculate the number of bits transferred in a frame of data ; Transmission process flag signal start_flag, Throughout every data transmission .

Code up ：

//date:2022.6.30
//edgar.yao
//uart_tx block


module uart_tx(
        input           clk,
        input           rst_n,
        input[7:0]      cmd_data,
        input           data_valid,

        output          tx,
        output          tx_read