VHDL implementation of arbitrary size matrix multiplication

VHDL Realize matrix multiplication of any size

You can modify the size of the matrix through parameters ;
Use VHDL Language implementation ;
stay vivado Synthesis and Simulation on .

The code is as follows ：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.DigEng.ALL;
entity Top_level is
------------set generic value for N,M,H,data_size--------------------
– Default values 23 matrix A and 32 matrix B to define the size of matrices
generic( M: natural := 3; – the number of columns of A and rows of B
N: natural := 5; – the number of columns of B
H: natural := 4; – the number of rows of A
data_size: natural := 5); – how many bits of binary number representing the data stored in ROM
---------------set inputs and outputs for the matrix multiplication--------
– Define ports in the circuits
Port ( CLK : in STD_LOGIC; – time sequence
RST :