[FPGA tutorial case 6] design and implementation of dual port RAM based on vivado core

FPGA Tutorial directory

MATLAB Tutorial directory

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1. Software version

vivado2019.2

2. Theoretical knowledge of this algorithm

        stay FPGA in ,RAM Is a very important module ,RAM Write from any specified address at any time when working （ Deposit in ） Or read out （ Take out ） Information .

and ROM similar , stay vivado in , New as follows IP nucleus

  The setting process is as follows ：

memory type Set to simple dual Port RAM

  PORT A Set as follows ( In practice, , The bit width of the data width And depth depth It can be adjusted as needed )：