[quick start of Digital IC Verification] 7. Basic knowledge of digital circuits necessary for verification positions (including common interview questions)

Reading guide ： The author has the honor to be a pioneer in the field of electronic information in China “ University of electronic technology ” During postgraduate study , Touch the cutting edge Numbers IC Verification knowledge , I heard something like Huawei Hisilicon 、 Tsinghua purple light 、 MediaTek technology And other top IC related enterprises in the industry , Pairs of numbers IC Verify some knowledge accumulation and learning experience . Want to get started for help IC Verified friends , After one or two thoughts , This column is specially opened , In order to spend the shortest time , Take the least detours , Most learned IC Verify technical knowledge .

Preface

This section will mainly introduce the following sections ：

• Fundamentals of digital circuits ：CMOS device
• Digital circuit power consumption
• Moore's law ：22nm FinFET process
• Digital combinational circuit logic device ： And gate 、 Or gate 、 Not gate
• Digital sequential circuit logic device ： register 、 Latch
• Digital circuit numerical representation
• Complement representation of digital circuits
• Digital Boolean logic

To be honest , This part is not used much for future verification Posts , But it's very useful for interviews , And these are also the basic qualities that a professional verification engineer should have , It is also one of the keys to distinguish whether or not they have a major background . One more thing to say is , Usually fresh students are interviewed , The distinction between design and verification is not too obvious , Therefore, we should expand the breadth of our knowledge system as much as possible , At the same time, we should also have the depth of verifying the knowledge system ！

One 、 Fundamentals of digital circuits ：CMOS device

COMS（Complementary Metal Oxide Semiconductor） Usually it means Complementary metal oxide semiconductor .

1.1、MOS The transistor

MOS The three-dimensional structure diagram of the transistor is as follows ：

A tube can be seen as 0 and 1 The basic unit of ！

1.2、CMOS Inverter

Usually MOS The tube is made of PMOS（P Express Positive） and NMOS（N Express Negative） Two types of , These two kinds of tubes are complementary , Together, it's called CMOS（C Express Complementary, Complementary ）.

1.2.1、CMOS The inverter consists of

PMOS and NMOS Will constitute the basic logic unit of the circuit , As shown in the figure below, the structure of the inverter （ Need to master ）.

• if In Input 0,NMOS Of Gate yes 0,NMOS In the off state ;PMOS Of Gate Through the inverter （ Small circles in the figure ） yes 1,PMOS on ; here Out And PMOS Of Source The end state is the same , namely Out Be pulled to VDD, Output 1.
• if In Input 1,NMOS It's on ,PMOS It's off ,Out And NMOS Of Drain The end state is the same , namely Out Be pulled to GND, Output 0.
• Sum up , This logic implements an inverter .

CMOS Corresponding standard unit （Standard Cell） Process drawings （ Or territory Layout）, As shown below ：

Common written questions ：PMOS Tube ratio NMOS What is the reason for the tube width ？

• answer ：PMOS It is hole conduction ,NMOS Tubes are electrically conductive , The mobility of electrons is about that of holes 2 times .

1.2.2、CMOS First order DC analysis of inverter

• left ：Vin = VDD, That is, the input is 1,N The pipe is open ,P The pipe is disconnected ,N The tube will have an on resistance .
• On the right side ：Vin = 0, That is, the input is 0,N The pipe is disconnected ,P The pipe is open ,P The tube will have an on resistance .

1.2.3、CMOS Inverter transient response

No matter from 1 To 0, Or from the 0 To 1, Both have a transition time , namely transient time, Not an ideal vertical jump . For all that , Our front-end analysis is still based on the ideal vertical jump . Because we pay more attention to high-level logical functions , Try not to be involved with the selection of the underlying process library , If this is coupled together, analysis will directly collapse people .

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1.2.4、CMOS Of the inverter transient time

Closer to reality transient time（ Capacitive reactance effect ）

A simplified version of transient time

1.2.4、CMOS Inverter summary

On the left is a layout of the back-end design , There's a PMOS Connect to VDD, Here's a NMOS Connect to GND.

Two 、 Digital circuit power consumption

2.1、Dynamic Power Consumption Dynamic power consumption

2.1.1、Charging and discharging capacitors Flip power consumption

Overturning of the pipe , Power consumption caused by the opening and closing of tubes ！

• Boosting can improve performance （CELL The delay will be shorter ,transient It gets shorter , The turning frequency can be higher ）, But at the same time, power consumption increases
• When the temperature rises , Increased power consumption
• From the above dynamic power consumption formula, we can see , Dynamic power consumption is independent of transistor size , Is proportional to the square of the voltage （

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Node Transition Activity and power Node switching activity and power

• When doing engineering, the final conclusion is derived , That is, the red framed part in the above figure . It is not difficult to draw a conclusion , Power consumption Average Mainly related to the square of voltage 、 It has something to do with the clock frequency .

2.1.2、Short Circuit Currents Short circuit power consumption

Short circuit path between supply rails during switching A short circuit is formed between the power supply and the ground at the moment when the switch is turned on （eg：CMOS When two tubes of the inverter are connected at the same time ）

• The second picture in the above figure , Assume voltage Vdd yes 5V, When the voltage is 2.5V Left and right , The short-circuit current reaches the maximum ！

Minimizing Short-Circuit Power Minimize short circuit power consumption

• It's not hard to see from the picture above , Supply voltage Vdd It is an important factor to determine the short-circuit power consumption .

2.2、Static Power Consumption Static power consumption

2.2.1、Leakage Leakage power consumption

Leaking diodes and transistors Diode and transistor leakage （ Form a path with the ground , But the current is very small ）

• The cause of the device itself will inevitably produce leakage current
• To solve the leakage power consumption is to put it Sub-Threshold Make some changes , Suppliers will provide many different libraries , Different libraries Sub-Threshold Dissimilarity .Sub-Threshold high , The frequency will be higher , The delay will be shorter , The corresponding leakage power consumption is larger .

2.3、Principles for Power Reduction The principle of reducing power consumption

• The most important thing to reduce power consumption is to reduce voltage , The second is to reduce the inversion rate （ Such as clock gating ）, Finally, reduce the capacitance ！

3、 ... and 、 Moore's law ：22nm FinFET process

Moore's law ： When the price is constant , The number of components that can be accommodated on an integrated circuit , About every 18-24 It doubles in two months , Performance will also double .

3.1、3D MOS The transistor 22nm

• FINFET（ Fin transistor ） Its structure is similar to shark fin , It was invented by a team led by Professor Zhengming Hu of the University of California , Mainly for breakthrough chips 25nm process , solve mosFET Due to the tunneling effect associated with process reduction .

Four 、 Combinational circuits and sequential circuits

The basic internal structure of the standard unit is introduced above , Including the principle of realizing basic logic , And its electrical characteristics , Including its capacitive impedance characteristics , It also introduces the content related to power consumption , Finally, the famous Moore's law in the industry is introduced . The next thing to learn is the logic of numbers , The correlation with the above electrical characteristics is not great . Electrical characteristics are more considered in the back-end physical implementation （eg： Capacitive reactance effect results from 0 To 1 Jumping takes time , Jumping will cause the tube to overturn and cause power consumption ）, Digital verification requires more understanding of the front-end logic （eg： Pure 0 To 1 Jumping , There will be no intermediate jump process ）！

4.1、 Digital combinational circuit logic device ： And gate 、 Or gate 、 Not gate

Combinational circuit means that the output is A timely response Of , The output at the current time is only related to the current input , Independent of previous input ！ The circuit realized by combinational logic is called combinational circuit .

Defects of combinational circuits ： Due to the difference of routing delay, combinatorial logic may Produce burrs , such Phenomenon is called competition , The result is called Adventure . To solve this problem , So it leads to Sequential logic ( Divide the time points into clock cycles , Collect data according to the clock cycle , Data collected in a stable state .)

4.1.1、 Combinational circuit （ Gate level circuit ）： NAND gate NAND

• The most basic thing in logic is called truth table （Truth table）： Traverse all the logic range values represented by the logic signal . Yes n If there is a bit 2 Of n Power state
• Truth table ,1 It's called 1 individual bit, In logic, a binary method is used . use cmos Take care of our circuit . One CMOS The input of the tube can only represent one digit or one bit, There are only two states 0 or 1, That is, the opening and closing of the pipe , It just matches the binary in Mathematics . There are just a few 2 Several power states of .
• And non （ Take non on the basis of and ）：A and B All for 1,out It's just 0

Common written questions ： Use NAND gate to design a circuit , Draw CMOS Circuit diagram of ！

• answer ： The picture on the right of the above picture .

NAND gate （NAND） Corresponding standard unit （Standard Cells）

• The circuit diagram on the right of the above figure is the circuit diagram implemented by the industry , The principle is the same as the previous circuit diagram , Just put two A/B The input of is connected together .
• On the left is the layout Layout！

4.1.2、 Combinational circuit （ Gate level circuit ）： Or not NOR

• Or not （ Take non on the basis of or ）：A and B All for 0,out It's just 1

4.2、 Digital sequential circuit logic device ： register 、 Latch

• Latch： Latch is level Sensitive devices

• Register： The register is edge-triggered Sensitive devices
  • Flip-Flop： Triggers are similar to registers

• Sequential circuits need clocks clk, There are two kinds of clock acquisition data ：Latch and Register.Register It's the most used , It uses the rising edge of the clock to pick （0->1 Is called rising edge ,1->0 It's called falling edge ）.
• Use the rising edge of the clock to pick , The data collected at the last point will always be maintained , This is also the characteristic of sequential circuits . You are required to enter D There can be no change from edge to edge , because Clk It is also the upper edge collection , This leads to setup The concept of , namely Set up time , amount to The data before the top edge of the clock should be stable .

4.2.1、Setup/Hold Time illustrations establish / Hold time diagram

• Set up time ： The rising edge of the clock comes Before , Keep the data stable for a long time ！

• Retention time ： The rising edge of the clock comes after , Keep the data stable for a long time ！

Frequently asked questions ： Why does a circuit need a trigger structure ？

• answer ： Trigger is used because trigger can save data , Save the circuit state ; The trigger is triggered at the edge of the clock , Using clock synchronization is to make the whole circuit work synchronously and uniformly ; The computation part of the multiplier is combinatorial logic , No trigger is required , The calculated results can be saved with triggers .

Frequently asked questions ： What is the establishment time 、 Retention time , If setup time violation （ The establishment time is not satisfied ） perhaps hold time violation （ Keep time unsatisfied ） What to do ？

• answer ： Set up time ： It refers to the arrival of the clock signal sampling edge of the trigger Before , Events in which data remains stable ; Retention time ： It refers to the channel at the sampling edge of the clock signal of the trigger after , Events in which data remains unchanged .

• Data establishment time and retention time

• The blue line in the above figure is the data path , The green line is the clock path , The source of both is the same .
• The above figure is a typical time series analysis model , In this model , Main analysis FF2 Data input of （B spot ） And clock input （ spot C）, Look at the relationship between the two , Is it satisfactory? Setup/Hold Time .
• Two D Clock source of trigger , All are A spot . There are some on the clock line BUFFER, To balance the clock tree , Try to make A The clock arrives at E Point and C The phase of the point is the same , The difference between the two ：|Tea - Tca| = Tskew.
• What we want to compare is FF2 Phase of data （B spot ） and CLK phase （C spot ） Relationship
  • B The phase of the point data and E spot CLK Phase is related .
  • from D Point to enter the data from F point out ,F The data pointed out is similar to E Dot CLK There is a certain delay between , We call it Tcq（Time Clk to Q）.
  • Data from F Click out to B spot , There will be a period of combinatorial logic between , This combinational logic also has a certain delay , We call it Tcomb（Time Combinational）, This combinational logic delay consists of two parts ： Device delay （ And or not ） And line delay .

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• Setup time violation：

  • The establishment time must meet the following conditions in static time series analysis
  • Tsetup < Clock delay - Data delay = (Tclk + Tca) - (Tea + Tcq + Tcomb) = Tclk + Tskew - Tcq - Tcomb
    • Why is there a clock delay path Tclk？CLK_E The rising edge of hits out the data , Only in CLK_C The next edge of collects data , That is to say Tclk+Tskew Collect data ！
  • If setup time violation, Then the above formula does not hold

• Setup time violation solution： Adjust the variables in the above formula ：Tclk、Tcomb、Tskew

  • increase Tclk
    • Reduce the working frequency of the digital system
  • Reduce Tcomb【 Most used in practical engineering 】
    • From the perspective of digital logic function design （ front end ）
      • Insert registers between combinational circuits , Add assembly line （pipeline）【 It is often used in practical engineering 】
        • The negative effect of increasing flow is that the delay of the whole process increases .
      • Without changing the logical function , Optimize combinational logic circuits 【 It is often used in practical engineering 】
      • Reduce fan out （fanout） Or load
    • From the perspective of digital physical layout implementation （ Back end ）
      • Replace faster standard units （HVT-High Vlotage Threshold,SVT-Standard Voltage Threshold,LVT-Low Voltage Threshold）, But the corresponding power consumption will also increase , Need to do Tradeoff！
      • Replace the standard unit with stronger driving capacity （X2,X4）
      • Replace the metal layer with lower resistance value to reduce the load of standard unit circuit and metal wire mesh delay
    • increase Tskew【 Less used in Engineering , It is easy to destroy clock trees 】
      • On the clock path , Insert Buffer, Increase the delay of the clock path , But it cannot affect Hold Timing

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• Hold time violation（ It has nothing to do with the clock cycle ）

  • The holding time must meet the following conditions during static time series analysis ：
  • Thold < Data delay - Tskew = Tcq + Tcomb - Tskew
  • If hold time violation, Then the above formula does not hold

• Hold time Violation solution

  • increase Tcomb
    • On the data transmission path of the combinational circuit , Insert delay unit （buffer）, Increase the delay of combinatorial logic ; But when the delay of combinational logic increases ,setup time Violations may occur . At this time, we need to do Balance （Balance）. From this we can see that setup and hold time It's mutual restriction .
  • Reduce Tskew
    • Clock tree adjustment , do Clock tree balance,hold It's easy to converge . because hold time It has nothing to do with the clock cycle ！

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summary

• Set up time ： It refers to the arrival of the clock signal sampling edge of the trigger Before , Events in which data remains stable ; Retention time ： It refers to the channel at the sampling edge of the clock signal of the trigger after , Events in which data remains unchanged .
• setup and hold It's mutual restriction , Repair hold after ,setup The margin of will become smaller or negative . So the higher the clock frequency ,setup and hold The more serious the mutual restriction , There may even be repairs setup after ,hold It will violate the rules ; Or fix it hold after ,setup Will violate the phenomenon .

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Frequently asked questions ： Why triggers exist setup and hold time The requirements of ？

• answer ： When designing triggers , We need to pay attention to several time characteristics of triggers , Only when these characteristics are met can the trigger work properly .

Frequently asked questions ： When setup and hold time violation occurs , What are the consequences ？

• answer ： The data collected along the clock edge is not accurate , It will lead to unstable logic settings , Produce metastable . Because it just means 0 and 1.

Frequently asked questions ： What is metastable ？ How to solve the problem of metastability in asynchronous circuit design ？

• answer ： The state in the circuit is not 0 Namely 1, Usually the result is certain , In case of violation, So the result is 0 perhaps 1 You won't be sure , This state is called metastable . Metastable state : When picking edges, you may pick 0 perhaps 1 This uncertain state of .
• The solution to metastability ： In a single circuit Take more shots , To reduce the probability of metastability , Not completely eliminate metastable .
• setup and hold In the synchronous circuit, tools can be used to constrain , So that the timing can meet . Because there is no way to establish a clock path in an asynchronous circuit , So there is no way to constrain in asynchronous circuits , Maybe there will be violation, Metastable state will occur .

4.2.2、 Assembly line technology （pipeline）

Combinatorial logic is too long , It can lead to Tsetup dissatisfaction , At this time, we may reduce combinatorial logic , The way is to join the assembly line （ Insert D trigger ）！

4.3、 Full adder

• requirement ： Can draw a truth table , Boolean algebra is also written down . I use more in written examination . In practice, it is directly used verilog Write the code directly .
• The difference between half adder and full adder is whether there is cin, No, it's half adder
• The code in the upper right corner of the above figure is Verilog Generated after synthesis ！

4.4、 Multiplier

• The multiplier can also consist of a basic and or not gate （CMOS circuit ） constitute .

4.5、 How to realize arithmetic logic unit in industry

How to express （ Design ） Digital arithmetic logic unit ？

• HDL（ Hardware description language Hardware Description Language）：Verilog/VHDL/SystemVerilog
• adder （+）, Multiplier （*）

How to convert the description code of digital arithmetic logic unit into a file that can be generated ？

• Logic comprehensive technology ：HDL Convert to Netlist（MAP become Standard Cell Output ）（ Gate level grid ）
• Physical layout design （Place Route Layout and wiring , abbreviation PR）：Netlist Turn into GDSII（ It can be used to generate layout files ）

4.6、Design at a corssroad System-on-Chip

• With the improvement of integration , We integrate the system into the chip , abbreviation SoC

4.7、IP - Intellectual Property

• There will be many integrated in the chip IP,IP Is to implement different modules

4.8、VLSI VLSI automatic layout and wiring

• Lots of colors , There are many layers

5、 ... and 、 Digital circuit numerical representation

5.1、 Number system of digital circuit

• Binary system ：binary

  • 0（ Low level ）,1（ High level ）
  • 1’b0,1’b1

• octal ：octonary

  • 1’o0,1’o1,1’o2,1’o3,1’o4,1’o5,1’o6,1’o7
  • 0~7

• Decimal system ：decimal

  • 1’d0,1’d1,1’d2,1’d3,1’d4,1’d5,1’d6,1’d7,1’d8,1’d9
  • 0~9

• Hexadecimal ：Hexadecimal

  • 1’h0,1’h1,1’h2,1’h3,1’h4,1’h5,1’h6,1’h7,1’h8,1’h9,1’ha,1’b,1’hc,1’hd,1’he,1’hf
  • 0~F/f
  • 8421 code

5.2、 Complement in digital circuit

• The values in the digital circuit are expressed by positive numbers , Negative numbers need to be represented by complements
  • The highest position is 1 Is for negative numbers ,0 Hours represent positive numbers
• The complement of a positive number is a positive number itself
• A negative complement ： The sign bit remains the same , All of the other bit reverse , then +1
  • eg：+5： The original code is 0101, The complement is 0101;-5： The original code is ：1101, The complement code is 1011.

5.3、 Boolean logic

• And logic &
  • All for 1 when , And the logical value is 1
  • There is a bit 0, And the logical value is 0
• Or logic ||
  • All for 0 when , Or the logic is 0
  • There is a bit 1 when , Or the logic is 1
    • | Arithmetic operator ;|| Logical operators ( Only for True And wrong False) Both represent or ; For single bitt, both are the same , Multibit is different .
      • If a = 3’b101,b = 3’b110, that c = a | b = 3’b111;
      • If a = 3’b101,b = 3’b110, that c = a || b = 3’b001;
    • Empathy ~ Arithmetic operator ,! Logical operators
• Illogical ：!
  • 0 The non logic of is 1
  • 1 The non logic of is 0

Reference resources

• Numbers IC Design verification - Autumn trick Guide
• MosFET/FinFET/GAFET —— How far can fin transistors go
• FinFET Detailed explanation of process technology
• FinFET（ Fin type MOSFET） brief introduction
• FinFET The principle and process of
• after FinFET Technological evolution of the times
• Why does a circuit have a trigger structure ？
• Original code 、 Inverse code 、 Complement code