[Verilog quick start of Niuke series] ~ multi function data processor, calculate the difference between two numbers, use generate... For statement to simplify the code, and use sub modules to realize

1. VL6 Multifunctional data processor

Title source ： Cattle from

1.1 Title Description

According to the indication signal select Different , For input signal a,b Implement different operations . Input signal a,b by 8bit Signed number , When select The signal is 0, Output a; When select The signal is 1, Output b; When select The signal is 2, Output a+b; When select The signal is 3, Output a-b.

1.1.1 Signal schematic diagram

1.1.2 Waveform diagram

nothing

1.1.3 Input description

clk： The system clock
rst_n： Reset signal , Low level active
a,b：8bit Signed number of bits wide
select：2bit Unsigned number of bits wide

1.1.4 Output description

c：9bit Signed number of bits wide

1.2 Their thinking

adopt case Statement completes the operation of multiple branches , according to select Different values can be distinguished .

1.3 Code implementation

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n) begin
           c <= 9'd0; 
        end
        else begin
            case (select)
                2'b00 : begin
                    c <= {
    a[7], a}; 
                end
                2'b01 : begin
                    c <= {
    b[7], b}; 
                end
                2'b10 : begin
                    c <= {
    a[7], a} + {
    b[7], b}; 
                end
                2'b11 : begin
                    c <= {
    a[7], a} - {
    b[7], b}; 
                end
                default : begin
                   c <= 9'd0; 
                end
            endcase
        end
    end
endmodule

1.4 The test file

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1.5 Simulation waveform

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=========================================================================

2. VL7 Find the difference between two numbers

Title source ： Cattle from

2.1 Title Description

According to the input signal a,b The size of the relationship , Solve the difference between two numbers ： Input signal a,b by 8bit Unsigned number of bits wide . If a>b, The output a-b, If a≤b, The output b-a.

2.1.1 Signal schematic diagram

2.1.2 Waveform diagram

nothing

2.1.3 Input description

clk： The system clock
rst_n： Reset signal , Low level active
a,b：8bit Unsigned number of bits wide

2.1.4 Output description

c：8bit Unsigned number of bits wide

2.2 Their thinking

It is similar to the first question , But there are only two cases of this topic , Direct use if The statement block is solved .

2.3 Code implementation

`timescale 1ns/1ns
module data_minus(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output  reg [8:0]c
);
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n) begin
           c <= 9'd0; 
        end
        else begin
            if(a > b) begin
               c <= a - b; 
            end
            else begin
               c <= b - a; 
            end
        end
    end
endmodule

2.4 The test file

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2.5 Simulation waveform

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=========================================================================

3. VL8 Use generate…for Statements simplify code

3.0 Preface

Title source ： Cattle from

3.0.1 Knowledge point

Investigate generate…for… Usage of , The old , Don't talk much , Poke an eye , Portal

3.1 Title Description

In a certain module It contains many similar continuous assignment statements , Please use generata…for Statement writing code , Replace the statement , The requirement cannot change the original module The function of .
Use Verilog HDL Realize the above functions and write testbench verification .

module template_module(
input [7:0] data_in,
output [7:0] data_out
);
assign data_out [0] = data_in [7];
assign data_out [1] = data_in [6];
assign data_out [2] = data_in [5];
assign data_out [3] = data_in [4];
assign data_out [4] = data_in [3];
assign data_out [5] = data_in [2];
assign data_out [6] = data_in [1];
assign data_out [7] = data_in [0];

endmodule

3.1.1 Signal schematic diagram

nothing .

3.1.2 Waveform diagram

nothing

3.1.3 Input description

data_in：8bit Unsigned number of bits wide

3.1.4 Output description

data_out：8bit Unsigned number of bits wide

3.2 Their thinking

The basic grammar of this question . Just look at the portal in the preface .

3.3 Code implementation

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);

    genvar i;
    generate
        begin : practice
            for(i = 0; i < 8; i = i+1) 
                assign data_out[i] = data_in[7-i];
        end
    endgenerate
endmodule

3.4 The test file

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3.5 Simulation waveform

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=========================================================================

4. VL9 Use sub modules to compare the size of three input numbers

4.0 Preface

Title source ： Cattle from

4.0.1 Knowledge point

Mutual calls between modules .

4.1 Title Description

In digital chip design , Usually, the relatively independent code that completes specific functions is written into sub modules , When necessary, it can be instantiated in the main module , In order to improve the reusability of code and the hierarchy of design , Convenient for subsequent modification .

Please write a sub module , Two will be entered 8bit Variable of bit width data_a,data_b, And the output data_a,data_b The smaller of . And instantiate in the main module , Realize the output of three 8bit Function of minimum value of input signal .

4.1.1 Signal schematic diagram

4.1.2 Waveform diagram

nothing

4.1.3 Input description

clk： The system clock
rst_n： Asynchronous reset signal , Low level active
a,b,c：8bit Unsigned number of bits wide

4.1.4 Output description

d：8bit Unsigned number of bits wide , Express a,b,c Minimum of

4.2 Their thinking

It is not difficult to call this module , Write modules separately （ In general , Different modules are written in different files , But it is also possible to write it in a file ）. Before you call , This module needs precedent ！！！

However, the error prone part of this question is , Submodules are written in sequential logic and combinational logic , The processing method is different in the main module , Let's take a closer look ：

1. If your sub module is written in temporal logic , Your main module must be instantiated three times , If you want to instantiate two comparisons 3 Inputs abc Words , You will happen 2 Two signals are in the same period T Under the , And the other signal is in the cycle T+1 Next , Cause more confusion .
2. If your sub module is written in combinatorial logic , Your main module can only instantiate 2 Secondary sub module , But you have to complete the action of two shots and wait , Finally output together .

4.3 Code implementation

4.3.1 Submodules are written in sequential logic

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
    wire [7:0] ab_min_reg;
    wire [7:0] ac_min_reg;
    
    sub_mod u1(
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(b),
        .c(ab_min_reg)
    );
    sub_mod u2(
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(c),
        .c(ac_min_reg)
    );
    sub_mod u3(
        .clk(clk),
        .rst_n(rst_n),
        .a(ab_min_reg),
        .b(ac_min_reg),
        .c(d)
    );
    

endmodule
// Sub module （ Sequential logic implementation ）
module sub_mod(
    input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
    
	output reg [7:0]c
);
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n) begin
           c <= 8'd0; 
        end
        else begin
            if(a >= b) begin
               c <= b; 
            end
            else begin
               c <= a; 
            end
        end
    end
endmodule

4.3.2 Submodules are written in combinatorial logic

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
    
    wire [7:0] tmp1;    // a b  The minimum value of 
    child_mod U0(
        .a        ( a ),
        .b        ( b ),
        .d        ( tmp1 )
    );
    
    wire [7:0] tmp2;    // a c  The minimum value of 
    child_mod U1(
        .a        ( tmp1 ),
        .b        ( c ),
        .d        ( tmp2 )
    );
    
    reg [7:0] d_reg;
    reg [7:0] d_reg2;
    always @ (posedge clk&nbs***bsp;negedge rst_n)
        begin
            if( ~rst_n ) begin
                d_reg <= 8'b0;
                d_reg2 <= 8'b0;
            end 
            else begin
                d_reg <= tmp2;
                d_reg2 <= d_reg;
            end 
        end
    assign d = d_reg2;

endmodule

module child_mod(
        input [7:0]a,
        input [7:0]b,
        output [7:0]d
    );
    assign d = (a>b) ? b : a;
endmodule

4.4 The test file

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4.5 Simulation waveform

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Statement

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