[play with FPGA learning 2 in simple terms ----- design skills (basic grammar)]

Basic grammar （ Comprehensive Verilog A collection of methods ）

The so-called comprehensive Verilog grammar , It refers to some grammars that can be implemented by hardware . frequently-used RTL The syntax is as follows ：
Module declaration ：module…endmodule.
Port declaration ：input,output,inout(inout The usage of , We need to pay attention to ）.
Signal type ：wire,reg,tri etc. ,integer Commonly used in for In the sentence （reg,wire Is the most commonly used , commonly tri and integer Used in test scripts ）.
Parameters are defined ：parameter.
Operator ： Various logical operators 、 Move operator 、 Arithmetic operators are mostly integrable （ notes ：=== And ！== It's not comprehensive ）
Comparative judgment ：if…else,case（casex,casez)…default…endcase.
Continuous assignment ：assign, Question mark expression （？：）.
always modular ： The sensitive meter can be level 、 Along the signal posedge/negedge; Usually and @ Continuous use .
begin…end ( Popular said , It is C In the language “{}”）.
Task definition ：task…endtask.
Loop statement ：for( And less , But using it in some specific designs will get twice the result with half the effort ）
Assignment symbol ：= and <=( Blocking and non blocking assignment , It is very particular in the specific design ）.
The comprehensive grammar is Verilog A small subset of available grammars , The essence of hardware design is to try to use the simplest sentences to describe the most complex hardware , This is the essence of hardware description language .

If…else And case analysis of sentences

The two structures are completely consistent

Two pieces of code ,EX1 Use if…else sentence ,EX2 Use case sentence .

//EX1
input clk;
input rst_n;
input[3:0] data;
output[2:0] add;
reg[2:0] add;
always @(posedge clk) begin
	if(!rst_n) begin
		add<=0;
		end
	else begin
		if(data<4) add<=1;
		else if (data<8) add<=2;
		else if(data<12) add<=3;
		else add<=4;
		end
end

// EX2
input clk;
input rst_n;
input[3:0] data;
output[2:0] add;
reg[2:0] add;
always @(posedge clk) begin
	if(!rst_n) begin
		add<=0;
		end
	else begin
		case(data)
		0,1,2,3: add<=1;
		4,5,6,7: add<=2;
		8,9,10,11: add<=3;
		12,13,14,15: add<=4;
		default: ;
		endcase
		end
end

chart 2.1 Sum graph 2.2 Namely if…else Statement and case After sentence synthesis RTL View . Single from RTL View , There are obvious differences between the results of the two after synthesis .if…else Tends to have priority structures , and case Is a parallel structure .
Next, let's take a look at the resources they occupy . The resource occupation of the two is basically the same , Even the average fan out is the same .

Look at their Technology Map Viewer, Separately shown 2.3 Sum graph 2.4 Shown . The two are exactly the same , therefore , To be clear , In this case ,if…else and else The final implementation of statements is parallel , And exactly the same .

The two structures are different

// if...else  Sample code 
input clk;
input rst_n;
input close ,wr, rd;
output[2:0] db;
reg[2:0] dbr;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		dbr<=3'd0;
		end
	else begin
		if(close) dbr <=3'b111;
		else if(rd) dbr <=3'b101;
		else if(wr) dbr <=3'b011;
		else dbr <= 3'd0;
	end
end
assign db =dbr;

// case  Sample code 
input clk;
input rst_n;
input close ,wr, rd;
output[2:0] db;
reg[2:0] dbr;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		dbr<=3'd0;
		end
	else begin
		case({close,rd,wr})
			3'b100:dbr <= 3'b111;
			3'b010: dbr <=3'b101;
			3'b001: dbr <=3'b011;
			default:dbr <= 3'do;
			endcase
	end
end
assign db =dbr;

For the above two codes , Analyze only from the code ,if…else It has priority ,case It's a parallel structure .
The resource consumption of the two is different , Then the final realization of the two is not necessarily different .

from RTL View view , The realization of the two is exactly as expected , One with priority , A parallel processing .

From the final layout and structure after wiring , and RTL The view is very close , These two sample codes are used if…else and case The structure of the final implementation is different .
From the previous strength analysis, this is not uncommon , The unexpected thing is to use if…else The structure resource consumption of the implementation is unexpectedly higher than case Less to come （ It is a relative term ）. Such a result seems to refute the so-called “ multi-purpose case sentence , To use less if…else sentence , Because implementing a prioritized structure is more resource consuming than a parallel structure ” The verdict of .

in addition , In this example, multiple if…if… The result of statement implementation will be similar to case The result of the statement is consistent .

// if...if....  Sample code 
input clk;
input rst_n;
input close ,wr, rd;
output[2:0] db;
reg[2:0] dbr;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		dbr<=3'd0;
		end
	else begin
	dbr <=3'd0;
	if({close,rd,wr}==3'b100) dbr<=3'b111;
	if({close,rd,wr}==3'b010) dbr <=3'b101;
	if({close,rd,wr}==3'b001) dbr <=3'b011;
	end
end
assign db =dbr;

Verilog Code optimization for sentence

Verilog Medium for Although the sentence is also comprehensive , But in RTL Level code is basically not used . On the one hand, it's because for The use of statements takes up a lot of hardware resources , On the other hand, sequential logic design is often used in design , be used for There are not many places to cycle .
Here is an example to illustrate for The result of the comprehensive implementation of circular statements .

module test_3(clk,rst_n,data,num);
input clk;
input rst_n;
input[12:0] data;   // Input 13 Road data 
output[15:0] num;   //13 The number of channels with high data level 
reg[3:0] i;
reg[15:0] num;
always @ (posedge clk) begin
	if(!rst_n) begin
		num <=0;
		end
	else begin
		for(i=0;i<13;i=i+1)     // use for Cycle through the calculation 
			if(data[i]) num<= num+1;
		end
	end
	endmodule

The purpose of this code is to calculate 13 The number of high-level pulse signals , Most people will feel that this task is entrusted to for It's best to do it in a cycle , however for The loop cannot complete this task .

I believe you have found the problem , Why every clock cycle for The loop only executes this num<=num+1 Well ？always Statement using non blocking assignment “<=” when , Is in always After that, assign the value to the register on the left , Therefore, the above situation appears . Write the following code again with blocking statements ：

module test_3(clk,rst_n,data,num);
input clk;
input rst_n;
input[12:0] data;   // Input 13 Road data 
output[15:0] num;   //13 The number of channels with high data level 
reg[3:0] i;
reg[15:0] num;
always @ (posedge clk) begin
	if(!rst_n) begin
		num =0;
		end
	else begin
		for(i=0;i<13;i=i+1)     // use for Cycle through the calculation 
			if(data[i]) num = num+1;
		end
	end
	assign numout = num;
	endmodule

The waveform simulated by the modified code is shown in the figure ：

This waveform shows that the modified code has achieved the experimental purpose . It seems for In this case, the statement is relatively easy , If not for The sentence is more complicated . But then again ,for The efficiency of sentence synthesis is not high , On the premise of not requiring high speed , Or would you rather use multiple clock cycles than for sentence .
Besides , Generally, non blocking assignment statements are used in temporal logic "<=", The style of the following code is actually undesirable . Hardware language cannot be like C Language pursues the simplicity of code one sidedly .

inout usage

As shown in the table , It indicates that under the same driving intensity , Two driven wire The type and tri Truth table of type variable .

If at some point inout Port has input , At this time, I just want to take this inout Port for output , Then conflict is inevitable , Refer to the truth table for what results will appear .
Here's a typical inout How to use the port ：

inout io_data;     //inout mouth 
reg out_data;    // Data to be output 
reg io_link;        //inout Mouth direction control 
assign io_data = io_link ? out_data : 1'bz;   // This is the key 

When inout When the port is used as an input port , Be sure to put it in the high resistance state , Let the io_link=0 that will do ; When inout When the port is used as an output , Then io_link =1, Yes out_data The assignment is OK .