Verilog daily question (vl8 uses generate... For statement to simplify code)

Title Description

In a certain module It contains many similar continuous assignment statements , Please use generata…for Statement writing code , Replace the statement , The requirement cannot change the original module The function of . 
module template_module( 
    input [7:0] data_in,
    output [7:0] data_out
);
    assign data_out [0] = data_in [7];
    assign data_out [1] = data_in [6];
    assign data_out [2] = data_in [5];
    assign data_out [3] = data_in [4];
    assign data_out [4] = data_in [3];
    assign data_out [5] = data_in [2];
    assign data_out [6] = data_in [1];
    assign data_out [7] = data_in [0];
    
endmodule

This question is quite simple , Mainly review it again generate Usage of

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);
 
    generate 
           genvar i;
        for(i = 0;i < 8;i =i+1) 
        begin : ggg
            assign data_out[i] = data_in[7-i];
        end
            
    endgenerate
 
endmodule

generate 
It can be done to module、reg、assign、always、task Wait for the statement or module to copy
You have to use genvar Declare a loop variable ; begin Need to label after （ That is, the label of the copied part ）; Must be in begin end I'm going to cycle through it 、 Copy .

endgenerate

a key ：

1、 Common uses include generate-for、generate-case and generate-if Three sentences .
2、 The key ：generate Statements can be easily repeated Instantiation module ！

3、 in the light of generate-for sentence , Loop variable i You have to use genvar Statement . And in for The assignment of the loop must use assgin perhaps always complete .（ At first, I didn't write assign That leads to mistakes ）

// See the example for the reuse of modules

HDLbits Bcdadd100 （generate example ）_ Don't come out again error My blog -CSDN Blog module top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum ); wire [99:0] cout_; // Instantiate an array bcd_fadd u_fadd(a[3:0],b[3:0],cin,cout_[0],sum[3:0]); generate genvar i; ...https://blog.csdn.net/NJUzzf98/article/details/123924652?spm=1001.2014.3001.5501