Understand chisel language thoroughly 08. Chisel Foundation (V) -- wire, REG and IO, and how to understand chisel generation hardware

Chisel Basics （ 5、 ... and ）——Wire、Reg and IO, And how to understand Chisel Build hardware

The conclusion of the previous article mentioned ,UInt、SInt and Bits All are Chisel type , They themselves do not directly represent hardware , Only by encapsulating them into Wire、Reg or IO Will generate a circuit . This matter can be understood in this way , Digital logic circuits are made up of wires 、 Logic gate 、 Registers and input / output （ Including clock and reset signal ） And so on , The connection corresponds to Wire, Logic gate corresponding operator , Registers correspond to Reg, Input output correspondence IO. So in Chisel How can they be used in ？ How to understand Chisel Generation circuit ？ Learn this article together .

Wire、Reg and IO

stay Chisel in ,Wire Used to represent combinatorial logic ,Reg Used to represent registers （D- Set of triggers ）, and IO Is used to represent the interface of a module （ For example, the pin of a specific integrated circuit ）. As mentioned earlier ,Wire、Reg and IO Can encapsulate any Chisel type , And of course Bundle and Vec.

stay Scala in , Variables are divided into var and val Two types of , The former is variable , The latter is immutable . And in the Chisel in , We just need to use val To describe the circuit , It's immutable Scala Variable , such as ：

val number = Wire(UInt())
val reg = Reg(SInt())

We can assign or reassign the value or expression to Wire、Reg or IO, Use of Chisel Operators are :=：

number := 10.U
reg := value - 3.U

This is obviously the same as Scala The assignment operator in = It's different . How to use these two operators ？ It's simple , stay establish When we use a hardware object Scala The operator =, And I'm giving What already exists When assigning or reassigning hardware objects , Just use Chisel The operator :=.

Combinatorial logical values can also be conditionally assigned , But you need to assign values to each branch of the condition . Otherwise , A latch will be introduced （latch）, This is a Chisel Compiler does not accept . The best way is to create Wire A default value is given when , therefore , The previous code is better written like this ：

val number = WireDefault(10.U(4.W))

Empathy , As mentioned before ,Chisel Will infer the required bit width for signals and registers , But it is better to specify the desired bit width when creating hardware objects . On most occasions , It is also best to give the register a known reset initialization value ：

val reg = RegInit(0.S(8.W))

RegInit and WireDefault not quite the same , The former refers to the value at reset , The latter refers to the default connection .

as for IO, Interface for declaring a module , The usage is usually as follows ：

val io = IO(new Bundle {
    
    val in_a = Input(UInt(8.W))
    val out_b = Output(UInt(8.W))
})

IO() It's a bundle Example ,bundle Inside is the input and output interface , Use them separately Input and Output encapsulation . Here is just a brief introduction , We will talk about it later .

How to understand Chisel Build hardware

We have so far , Some have been lifted Chisel The basic code of , It looks like traditional programming languages, such as C and Java This kind is almost . however ,Chisel Like other hardware description languages , It really defines hardware components . What's the difference ？ In software , The code is executed line by line , In hardware, all lines of code are Parallel execution Of .

Write Chisel Be sure to keep in mind Chisel It's really hardware generation . You can imagine , Or draw on paper , We wrote them one by one Chisel Circuit description generated module . Create one component at a time , Will add a hardware , Each assignment statement , Will generate a gate circuit and / Or trigger .

So technically ,Chisel When executing code , It's Executive Scala Program , And then by executing Chisel sentence , aggregate （collect） All hardware components and connect these nodes . The network composed of these hardware nodes is Chisel Generated hardware , Can be born Verilog Code for ASIC or FPGA comprehensive , It can also be used. Chisel tester To test . The network composed of these hardware nodes is completely parallel ！

It may be a little difficult for people who have written software before to understand this kind of parallel execution , Because it is different from the parallel program of software , Hardware is naturally parallel , There is no need to assign programs to threads , There is no need to lock the communication between threads , It is a very simple parallel execution , The current runs simultaneously in every part of the hardware , That's it .

Conclusion

When I first came into contact with hardware description language , I'm confused, too , Often use the thinking of writing software to write hardware , The last thing I wrote is not what I imagined . You can only stop thinking about writing software , Simply understand writing hardware as building blocks , What we need to do is to logically connect them .

up to now , We haven't run the code yet , Just learned the basics Chisel grammar . Next article , We will learn how to use sbt Build our Chisel Project and run , At the same time, it also briefly introduces Chisel Tool flow for , Coming soon .