OC and OD gate circuit

Students who have studied digital and analog electricity , I should have heard of it all OC Gate circuit and OD Gate circuit . Even if you haven't heard of it , Then when I graduated and went for a job interview , May be asked by the interviewer or in the exam . Because many chips IO mouth , Its interior belongs to OC perhaps OD door . Think of last year , When the editor is interviewing for a job , The interviewer has asked this question , It was called a “ Miserable ” ah ！

As a hardware engineer , Although in circuit design , This kind of circuit is rarely encountered , But its circuit form and working principle must be understood .

So Xiaobian still needs to talk about OC Door and OD door .

OC door

OC The collector of the gate is open . That is, the collector of the triode is not connected . When the left end input is low , The output of the triode at the right end is low . However, when the left end input high level , Because the collector of the triode at the right end is in an open circuit state , Therefore, high level cannot be output . Therefore, if you want to output a high level on the right side, you need to pull up the resistance and external power supply to meet the high level output .

here ：

1. The input is high power level ,Q1 Conduction , here A Point is in low level , Unable to meet Q2 Conduction , Now Q2 To break off , The output is high level .
2. The input is low power level ,Q1 To break off , here A Point is in high level ,Q2 Conductive , At this time, the output voltage is low .
   OC The door uses a pull-up resistor to output a high level . Selection of resistance , We should choose from the principle of driving current and reducing power consumption .

The figure shows the simulated waveform

We will find that there is a downward pulse , At this time, a suitable capacitor can be added to solve this kind of problem .

Simulation oscillogram

OD door

The understanding idea is the same as that of open collector .

OD The gate is open drain . That is, the rightmost MOS The drain of the tube is not connected to anything . When the left end input is low , Right end MOS The tube output is low . However, when the left end input high level , Due to the MOS The tube drain is open , Therefore, high level cannot be output . Therefore, if you want to output a high level on the right side, you need to pull up the resistance and external power supply to meet the high level output .

This figure is the waveform of simulation , There will be a small number of pulses , The voltage is about 0.5V Rise .

To avoid this problem , Try adding a suitable capacitor at the output , To remove this interference . The addition of capacitance will also appropriately reduce the rising speed of level conversion . At the same time, the choice of pull-up resistance is also a factor that determines the rising speed . according to RC The delay circuit knows , resistance , The greater the capacitance , The lower the rising speed , However, resistance has the advantage of reducing power consumption . Therefore, the selection of the pull-up resistance value , Still need to balance power consumption and rising speed .

Capacitive effect ：