Verilog daily question (vl14 vending machine 1 -- FSM common question types)

  Vending machines

Title Description ：    

Design an automatic vending machine , There are three kinds of input currencies , by 0.5/1/2 element , What is the price of the drink 1.5 element , Ask for change , Change will only pay 0.5 element .

ps: The input currency will automatically pass through the edge detection and output one from the rising edge of the clock to 1, On the falling edge to 0 Pulse signal of

Be careful rst by Low level reset

Signal schematic diagram ：

d1   0.5 element

d2   1 element

d3   2 element

out1 drinks

out2 small change

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The first thought of this problem is the state machine , So first put State diagram Draw out ：

It seems a little complicated ...  It's much easier to write code according to the state diagram .

The details of the successfully compiled code are as follows ：（ But there are doubts in the period of state change ）

//A:nstate <= (d1)? B:(d2)?C:(d3)?E:nstate; 
// Here is a point that I don't understand , If you put the last nstate It's written in A Will report a mistake ,out1 Some values will be lost , But clearly d1d2d3 All for 0 when , Is to keep A Keep it the same ,nstate=A No problem, it should .（ See the answer to change nstate）

module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
// This question should use FSM To do it 
// Statement 7 Status 
    parameter A=0,B=1,C=2,D=3,E=4,F=5,G=6;
    reg [2:0] state,nstate;
    
// Logical change 
    always @(*) begin
        case(state)  
            A:nstate <= (d1)? B:(d2)?C:(d3)?E:nstate; 
// Here is a point that I don't understand , If you put the last nstate It's written in A Will report a mistake , But clearly d1d2d3 All for 0 when , Is to keep A Keep it the same ,nstate=A No problem, it should 
            B:nstate <= (d1)? C:(d2)?D:(d3)?F:nstate;
            C:nstate <= (d1)? D:(d2)?E:(d3)?G:nstate;
            D:nstate <= A;
            E:nstate <= A;
            F:nstate <= A;
            G:nstate <= A;
            default: nstate <= A;
        endcase
    end
  // Timing changes           
    always @(posedge clk or negedge rst)begin
        if(!rst) state<=A;
        else state<=nstate;
     end
            // Output decision 
            always @(*)begin 
                case(state)  // Output only when there is a rising edge of the answer , And press nstate To make output judgment 
                    D: begin out1<=1;out2<=0; end
                    E: begin out1<=1;out2<=1; end
                    F: begin out1<=1;out2<=2; end
                    G: begin out1<=1;out2<=3; end
                    default: begin out1<=0;out2<=0; end
                endcase
            end     
//*************code***********//
endmodule

In the answer, you can also see that simple registers are used to determine , That is, to judge by adding and counting , It seems to be a good idea , And the code will be much simpler .

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